Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10050016-B2
Application number	US-201715627957-A
Country	US
Kind code	B2
Filing date	Jun 20, 2017
Priority date	Oct 4, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole; a first component disposed in the through-hole; a second component disposed in the through-hole and attached to the first component; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the first component and side surfaces of the second component; a second connection member disposed on the first connection member and the first component; and a third connection member disposed on the first connection member and the second component. A number of at least one of the first or second components is plural, the second and third connection members are connected to each other through the first connection member, and the first connection member includes a redistribution layer electrically connected to a redistribution layer of the second connection member and a redistribution layer of the third connection member.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a first connection member having a through-hole;
a first component disposed in the through-hole;
a second component disposed in the through-hole and attached to the first component;
an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the first component and side surfaces of the second component;
a second connection member disposed on the first connection member and the first component and including a redistribution layer electrically connected to the first component; and
a third connection member disposed on the first connection member and the second component and including a redistribution layer electrically connected to the second component,
wherein a number of at least one of first or second components is plural,
the second and third connection members are connected to each other through the first connection member, and
the first connection member includes a redistribution layer electrically connected to the redistribution layer of the second connection member and the redistribution layer of the third connection member.

2. The fan-out semiconductor package of claim 1 , wherein a plurality of second components are attached to the first component.

3. The fan-out semiconductor package of claim 2 , wherein the first component is a first semiconductor chip having an active surface, having connection pads disposed thereon, and an inactive surface opposing the active surface, and
the plurality of second components are attached to the inactive surface of the first semiconductor chip.

4. The fan-out semiconductor package of claim 3 , wherein the plurality of second components are located on the inactive surface of the first semiconductor chip.

5. The fan-out semiconductor package of claim 3 , wherein the plurality of second components include second and third semiconductor chips, each having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, and
the second and third semiconductor chips are attached to the inactive surface of the first semiconductor chip so that the inactive surfaces thereof face the inactive surface of the first semiconductor chip.

6. The fan-out semiconductor package of claim 5 , wherein the plurality of second components further include a passive component.

7. The fan-out semiconductor package of claim 3 , wherein the plurality of second components are a plurality of passive components.

8. The fan-out semiconductor package of claim 1 , wherein a plurality of second components are attached to a plurality of first components, respectively.

9. The fan-out semiconductor package of claim 8 , wherein the plurality of first components include first and second semiconductor chips, each having active surface having connection pads disposed thereon and an inactive surface opposing the active surface,
the plurality of second components include third and fourth semiconductor chips, each having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, and
the third and fourth semiconductor chips are attached to the inactive surfaces of the first and second semiconductor chips, respectively, so that the inactive surfaces thereof face the inactive surfaces of the first and second semiconductor chips, respectively.

10. The fan-out semiconductor package of claim 1 , further comprising:
a first passivation layer disposed on the second connection member;
a second passivation layer disposed on the third connection member;
an underbump metal layer disposed in openings formed in the first passivation layer or openings formed in the second passivation layer; and
connection terminals disposed on the underbump metal layer,
wherein at least one of the connection terminals is disposed in a fan-out region that is a region does not overlap, in a direction along which the second component is attached to the first component, with one of the first and second components having a largest area.

11. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer, opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and
the first and second redistribution layers are electrically connected to the first and second components.

12. The fan-out semiconductor package of claim 11 , wherein the first connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and
the third redistribution layer is electrically connected to the first and second components.

13. The fan-out semiconductor package of claim 12 , wherein the second redistribution layer is disposed on a level between the second and third connection members, and
the second redistribution layer is not in contact with the second and third connection members.

14. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
the first to third redistribution layers are electrically connected to the first and second components.

15. The fan-out semiconductor package of claim 14 , wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and
the fourth redistribution layer is electrically connected to the first and second components.

16. The fan-out semiconductor package of claim 14 , wherein the second redistribution layer is disposed on a level between the second and third connection members, and
the second redistribution layer is not in contact with the second and third connection members.

17. A fan-out semiconductor package comprising:
a first connection member having a through-hole and including a first redistribution layer;
a first electronic component and a second electronic components stacked on each other in the through-hole of the first connection member, each of the first and second electronic components having electric contacts;
a second connection member including a second redistribution layer; and
a third connection member including a third redistribution layer,
wherein the first connection member, the first electronic component, and the second electronic component are disposed between the second connection member and the third connection member,
the electric contacts of the first electronic component face the second connection member and are electrically connected to the second redistribution layer of the second connection member,
the electric contacts of the second electronic component face the third connection member and are electrically connected to the third redistribution layer of the third connection member, and
the second and third redistribution layers are electrically connected to each other at

Assignees

• Samsung Electro Mech

Inventors

• Lee Sang Jin
• Jang Min Seok

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title