Fan-out stacked system in package (SIP) and the methods of making the same

US9601463B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9601463-B2
Application numberUS-201414327203-A
CountryUS
Kind codeB2
Filing dateJul 9, 2014
Priority dateApr 17, 2014
Publication dateMar 21, 2017
Grant dateMar 21, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a package, the method comprising: forming one or more first fan-out redistribution layers (RDLs) comprising a conductive line; forming a fan-out tier over the one or more first fan-out RDLs, wherein forming the fan-out tier comprises: forming a first through intervia (TIV) over the one or more first fan-out RDLs; bonding a first device die to the one or more first fan-out RDLs; dispensing a first molding compound around the first device die and the first TIV; and exposing first connectors on the first device die and the first TIV, a topmost surface of the TIV being level with topmost surfaces of the first connectors; forming one or more second fan-out RDLs over the fan-out tier, wherein the first TIV electrically connects the one or more second fan-out RDLs to the one or more first fan-out RDLs; bonding a second device die to the one or more second fan-out RDLs using second connectors, the second connectors being interposed between the second device die and the one or more second fan-out RDLs, wherein the one or more second fan-out RDLs electrically connects the first and the second device dies; after bonding the second device die to the one or more second fan-out RDLs, patterning the one or more first fan-out RDLs to expose the conductive line; and disposing an external connector on the conductive line, wherein the external connector is at least partially disposed in the one or more first fan-out RDLs. 2. The method of claim 1 wherein forming the first TIV comprises: disposing a photoresist over the one or more first fan-out RDLs; patterning an opening in the photoresist; filling the opening with a conductive material; and removing the photoresist. 3. The method of claim 2 , wherein forming the first TIV further comprises disposing seed layer between the photoresist and the one or more first fan-out RDLs, wherein the opening exposes the seed layer, and wherein filling the opening comprises using the seed layer in a uni-directional electroless or electrochemical plating process. 4. The method of claim 1 , wherein patterning the one or more first fan-out RDLs to expose the conductive line comprises laser drilling. 5. The method of claim 1 , wherein bonding the first device die comprises adhering the first device die to the one or more first fan-out RDLs using an adhesive layer on a backside of the first device die. 6. The method of claim 1 , further comprising: forming a second TIV over the one or more second fan-out RDLs; dispensing a second molding compound around the second device die and the second TIV; exposing the second TIV; forming one or more third fan-out RDLs over the second TIV and the second device die, wherein the second TIV electrically connects the one or more third fan-out RDLs to the one or more second fan-out RDLs; and bonding a third device die to the one or more third fan-out RDLs, wherein the one or more third fan-out RDLs electrically connects the first and the third device dies. 7. A method for forming a package, the method comprising: forming one or more first redistribution layers (RDLs) over a carrier; attaching a first device die to the one or more first RDLs; dispensing a first molding compound over the first device die and the one or more first RDLs, the first molding compound extending along a sidewall of the first device die; forming one or more second RDLs over the first device die and the first molding compound, the one or more second RDLs being electrically coupled to the first device die; attaching a second device die to the one or more second RDLs, the one or more second RDLs being electrically coupled to the second device die, the one or more second RDLs being interposed between the first device die and the second device die; dispensing a second molding compound over the second device die and the one or more second RDLs, the second molding compound extending along a sidewall of the second device die; forming one or more third RDLs over the second device die and the second molding compound; attaching a third device die to the one or more third RDLs, the one or more third RDLs being electrically coupled to the third device die, the one or more third RDLs being interposed between the second device die and the third device die; dispensing a third molding compound over the third device die and the one or more third RDLs, the third molding compound extending along a sidewall of the third device die; and debonding the carrier from the one or more first RDLs. 8. The method of claim 7 , further comprising: after debonding the carrier, patterning the one or more first RDLs to expose at least one conductive feature; and disposing an external connector on the at least one conductive feature, wherein the external connector is at least partially disposed in the one or more first RDLs. 9. The method of claim 7 , further comprising: forming a first via over the one or more first RDLs, the first via extending through the first molding compound and electrically coupling the one or more first RDLs and the one or more second RDLs; and forming a second via over the one or more second RDLs, the second via extending through the second molding compound and electrically coupling the one or more second RDLs and the one or more third RDLs. 10. The method of claim 7 , wherein attaching the first device die to the one or more first RDLs comprises attaching a backside of the first device die to the one or more first RDLs using an adhesive. 11. The method of claim 7 , wherein attaching the second device die to the one or more second RDLs comprises bonding a front side of the second device die to the one or more second RDLs using a plurality of connectors. 12. The method of claim 7 , wherein attaching the third device die to the one or more third RDLs comprises bonding a front side of the third device die to the one or more third RDLs using a plurality of connectors. 13. The method of claim 7 , wherein attaching the second device die to the one or more second RDLs comprises bonding the second device die to the one or more second RDLs using a plurality of connectors, the plurality of connectors being interposed between the second device die and the one or more second RDLs. 14. A method for forming a package, the method comprising: attaching a first side of a first device die to a carrier; dispensing a first molding compound over the carrier, the first molding compound contacting a sidewall of the first device die; forming one or more first RDLs over a second side of the first device die, the second side of the first device die being opposite the first side of the first device die; attaching a first side of a second device die to the one or more first RDLs, the one or more first RDLs being interposed between the first device die and the second device die; dispensing a second molding compound over the one or more first RDLs, the second molding compound contacting a sidewall of the second device die; forming one or more second RDLs over a second side of the second device die, the second side of the second device die being opposite the first side of the second device die; attaching a first side of a third device die to the one or more second RDLs, the one or more second RDLs being interposed between the second device die and the third device die; dispensing a third molding compound over the one or more second RDLs, the third molding compound contacting a sidewall of the third device die; forming one or more third RDLs over a second side of the third device die, the second side of the third device die being opposite the first side of the

Assignees

Inventors

Classifications

  • used as a support during the manufacture of self-supporting substrates · CPC title

  • used as a support during manufacture of interconnect decals or build up layers · CPC title

  • using temporarily an auxiliary support · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9601463B2 cover?
An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device di…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).