3DIC package and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9496249-B2
Application number	US-201514925404-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Dec 13, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding material, and a redistribution line over the first molding material. The redistribution line is electrically connected to the TV. A second device die is over and bonded to the first device die through flip-chip bonding. A second molding material molds the second device die therein.

First claim

What is claimed is:

1. A method comprising:
placing a first device die over a carrier;
molding the first device die and a plurality of conductive features in a first molding material;
grinding the first molding material to expose first ends of the plurality of conductive features and metal pillars of the first device die;
forming a first plurality of redistribution lines over and electrically connected to the metal pillars and the plurality of conductive features;
forming electrical connectors over and electrically connected to the metal pillars;
bonding a second device die to the electrical connectors;
molding the second device die in a second molding material;
adhering a third device die to a back surface of the second device die through an adhesive; and
encapsulating the third device die in a third encapsulating material.

2. The method of claim 1 further comprising:
detaching the first device die and the first molding material from the carrier;
grinding the first molding material to expose second ends of the plurality of conductive features; and
forming a second plurality of redistribution lines electrically connected to the plurality of conductive features, wherein the first plurality of redistribution lines and the second plurality of redistribution lines are on opposite sides of the first molding material.

3. The method of claim 1 further comprising preparing the first device die comprising:
forming the metal pillars over and electrically connected to an interconnect structure of the first device die; and
covering the metal pillars with a dielectric layer, wherein the dielectric layer fills gaps between the metal pillars, and wherein during the grinding the first molding material, the dielectric layer is grinded.

4. The method of claim 3 , wherein after the grinding of the first molding material, the metal pillars are exposed.

5. The method of claim 1 further comprising, before the molding of the first device die:
forming a seed layer over the carrier;
forming a mask layer over the seed layer;
patterning the mask layer to form openings, wherein the seed layer is exposed through the openings;
forming the plurality of conductive features in the openings; and
removing the mask layer and portions of the seed layer overlapped by the mask layer.

6. The method of claim 1 further comprising:
bonding a third device die to the first device die through flip-chip bonding, wherein the third device die is molded in the second molding material.

7. The method of claim 1 , wherein the plurality of conductive features comprises a non-solder material.

8. The method of claim 1 , wherein the adhesive is in contact with both the second device die and the second molding material.

9. A method comprising:
encapsulating a first device die and a first plurality of conductive features in a first encapsulating material, wherein the molded first plurality of conductive features form a first plurality of Through Vias (TVs), wherein the first device die comprises:
a first semiconductor substrate; and
a first interconnect structure overlying the first semiconductor substrate;

forming a first plurality of redistribution lines over the first encapsulating material, wherein the first plurality of redistribution lines is electrically connected to the first plurality of TVs and the first device die;
bonding a second device die to the first plurality of redistribution lines through flip-chip bonding, the second device die comprising:
a second semiconductor substrate; and
a second interconnect structure underlying the second semiconductor substrate;

encapsulating the second device die in a second encapsulating material;
adhering a third device die to a back surface of the second device die through an adhesive;
forming a second plurality of conductive features over and electrically coupled to the first plurality of redistribution lines;
encapsulating the adhesive, the third device die, and the second plurality of conductive features in a third encapsulating material, wherein the molded second plurality of conductive features form a second plurality of TVs; and
forming a second plurality of redistribution lines over the third encapsulating material and electrically connected to the second plurality of TVs.

10. The method of claim 9 , wherein the second plurality of TVs continuously extend from a top surface of the third encapsulating material to a bottom surface of the second encapsulating material, with no distinguishable interface therein.

11. The method of claim 9 , wherein a bottom surface of the first encapsulating material is coplanar with a bottom surface of the first semiconductor substrate.

12. The method of claim 9 further comprising plating a non-solder metallic material to form the first plurality of conductive features.

13. The method of claim 9 , wherein the first device die comprises:
a metal pillar; and
a dielectric layer, wherein the encapsulating of the first device die and the first plurality of conductive features comprises a planarization to make a top surface of the metal pillar and a top surface of the dielectric layer to be coplanar with a top surface of the first encapsulating material.

14. The method of claim 9 further comprising forming a third plurality of redistribution lines underlying the first encapsulating material, wherein the third plurality of redistribution lines is electrically connected to the first plurality of TVs.

15. The method of claim 9 further comprising:
bonding a fourth device die to the third device die through flip-chip bonding; and
encapsulating the fourth device die in a fourth encapsulating material.

16. The method of claim 9 , wherein the first encapsulating material and the second encapsulating material are different from each other.

17. A method comprising:
placing a first device die over a carrier;
encapsulating the first device die in a first encapsulating material;
planarizing the first encapsulating material to expose a plurality of metal pillars of the first device die;
forming a first plurality of redistribution lines over and electrically connected to the plurality of metal pillars;
forming electrical connectors over and electrically connected to the metal pillars, wherein the electrical connectors comprise solder regions;
bonding a second device die to the solder regions;
encapsulating the second device die in a second encapsulating material;
adhering a third device die to a back surface of the second device die through an adhesive; and
encapsulating the third device die in a third encapsulating material.

18. The method of claim 17 further comprising:
forming a plurality of conductive features over a carrier; and
encapsulating the plurality of conductive features in the first encapsulating material.

19. The method of claim 18 further comprising:
detaching the first device die and the first encapsulating material from the carrier;
grinding the first encapsulating material to expose second ends of the plurality of conductive features; and
forming a second plurality of redistribution lines electrically connected to the plurality of conductive features, wherein the first plurality of redistribution lines and the second plurality of redistribution lines are on opposite sides of the first encapsulating material.

20. The method of claim 17 wherein the first device die comprises a dielectric layer encircling the metal pillar, wherein after the planarizing of the first encapsulating material, a top surface

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Kim Hong
• Huang Szu-Po
• Jeng Shin-Puu
• Hung Wensen

Classifications

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P14/46

  using a liquid · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title