Device having an air gap adjacent to a contact plug and covered by a doped dielectric layer

Patent metadata

Field	Value
Publication number	US-12432963-B2
Application number	US-202418402173-A
Country	US
Kind code	B2
Filing date	Jan 2, 2024
Priority date	Aug 30, 2019
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

First claim

What is claimed is:

1. A device comprising:
an epitaxial source/drain region over a substrate;
a first dielectric layer over the epitaxial source/drain region;
a second dielectric layer over the first dielectric layer and over the epitaxial source/drain region, wherein the second dielectric layer comprises an upper region having a higher dopant concentration than a lower region; and
a contact plug extending through the second dielectric layer and contacting the epitaxial source/drain region, wherein the contact plug is separated from the first dielectric layer and the lower region of the second dielectric layer by an air gap, wherein the upper region of the second dielectric layer extends across the air gap and physically contacts the contact plug.

2. The device of claim 1 , wherein the contact plug comprises a spacer layer that is exposed by the air gap.

3. The device of claim 1 , wherein an upper region of the epitaxial source/drain region is exposed by the air gap.

4. The device of claim 3 , wherein the upper region of the epitaxial source/drain region and the upper region of the second dielectric layer comprise the same dopant.

5. The device of claim 1 further comprising a third dielectric layer over the second dielectric layer, wherein a lower portion of the third dielectric layer protrudes into the second dielectric layer, wherein the lower portion of the third dielectric layer extends over the air gap.

6. The device of claim 1 , wherein the second dielectric layer comprises silicon oxide.

7. The device of claim 1 , wherein the air gap has a width in the range of 0.5 nm to 4 nm.

8. The device of claim 1 , wherein the upper region of the second dielectric layer has a maximum dopant concentration that is between 1 nm and 5 nm below a top surface of the second dielectric layer.

9. A semiconductor device comprising:
a gate structure adjacent to a contact plug;
a first dielectric layer over the gate structure, wherein the first dielectric layer comprises a first region that is doped with a first dopant, wherein the first region physically contacts a sidewall of the contact plug; and
an air gap between the gate structure and the contact plug, wherein the first region seals a top of the air gap, wherein a thickness of the first dielectric layer over the gate structure is greater than a thickness of the first dielectric layer over the air gap.

10. The semiconductor device of claim 9 , wherein the first region extends over the gate structure.

11. The semiconductor device of claim 9 , wherein a height of the air gap is greater than a height of the gate structure.

12. The semiconductor device of claim 9 , wherein the thickness of the first dielectric layer over the gate structure is in the range of 10 nm to 30 nm.

13. The semiconductor device of claim 9 further comprising a gate spacer layer between the gate structure and the air gap.

14. The semiconductor device of claim 9 , wherein the first dopant comprises at least one of germanium, argon, silicon, or xenon.

15. The semiconductor device of claim 9 further comprising a second dielectric layer over the first dielectric layer and the contact plug, wherein the second dielectric layer comprises the first dopant.

16. A device comprising:
a contact plug over a substrate, wherein the contact plug comprises an upper portion and a lower portion;
an air gap laterally surrounding the lower portion of the contact plug;
an insulating layer laterally surrounding the upper portion of the contact plug, wherein the insulating layer comprises a doped portion, wherein the doped portion covers the air gap; and
a capping layer extending over the insulating layer and the contact plug.

17. The device of claim 16 , wherein a top surface of the insulating layer and a top surface of the contact plug are level.

18. The device of claim 16 , wherein the capping layer laterally surrounds the upper portion of the contact plug.

19. The device of claim 16 further comprising a gate structure that is laterally separated from the contact plug by the air gap.

20. The device of claim 19 , wherein a thickness of the insulating layer over the gate structure is greater than a thickness of the insulating layer over the air gap.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Su-Hao
• Chen Kuo-Ju
• LEE Kai-Hsuan
• Wong I-Hsieh
• Yang Cheng-Yu
• Chen Liang-Yin
• Chang Huicheng
• Yeo Yee-Chia
• Jang Syun-Ming
• Chou Meng-Han

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P30/22

  using masks · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title