Complementary tunneling fet devices and method for forming the same

Patent metadata

Field	Value
Publication number	US-2016268401-A1
Application number	US-201315036058-A
Country	US
Kind code	A1
Filing date	Dec 26, 2013
Priority date	Dec 26, 2013
Publication date	Sep 15, 2016
Grant date	—

Abstract

Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions. Another type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type organic semiconductor material; a doped second region, formed above the substrate, having n-type oxide semiconductor material; and a gate stack coupled to the doped source and drain regions. In another example, TFET is made using organic only semiconductor materials for active regions.

First claim

1 . A tunneling field effect transistor (TFET), comprising:
a substrate; a doped first region, disposed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table; a doped second region, disposed above the substrate, having transparent or semi-transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions.

2 . The TFET of claim 1 , wherein the transparent or semi-transparent oxide n-type semiconductor material is selected from a group consisting of α-Ga 2 —O 3 , β-Ga 2 —O 3 , In 2 O 3 , and SnO 2 .

3 . The TFET of claim 1 , wherein the TFET is a FinFET, Tri-Gate, or square nano-wire based device.

4 . The TFET of claim 1 further comprises a lightly doped n-type material coupled to the gate stack, the lightly doped n-type material separating the first and second doped regions from one another.

5 . The TFET of claim 1 further comprises a lightly doped p-type material coupled to the gate stack, the lightly doped p-type material separating the first and second doped regions from one another.

6 . The TFET of claim 1 , wherein the doped first region is a source region, and wherein the doped second region is a drain region.

7 . A tunneling field effect transistor (TFET), comprising:
a substrate; a doped first region, disposed above the substrate, having p-type organic semiconductor material; a doped second region, disposed above the substrate, having n-type transparent or semi-transparent oxide semiconductor material; and a gate stack coupled to the doped source and drain regions.

8 . The TFET of claim 7 , wherein the p-type organic semiconductor material is selected from a group consisting of P3HT, MDMO-PPV, PEFOT:PSS, CoPc, and CuPc.

9 . The TFET of claim 7 , wherein the n-type transparent or semi-transparent oxide semiconductor material is selected from a group consisting of α-Ga 2 —O3, β-Ga 2 —O 3 , In 2 O 3 , and SnO 2 .

10 . The TFET of claim 7 , wherein the TFET is a FinFET, Tri-Gate, or square nano-wire based device.

11 . The TFET of claim 7 further comprises a lightly doped n-type material coupled to the gate stack, the lightly doped n-type material separating the doped first and second regions from one another.

12 . The TFET of claim 7 further comprises a lightly doped p-type material coupled to the gate stack, the lightly doped p-type material separating the doped first and second regions from one another.

13 . The TFET of claim 12 , wherein the lightly doped p-type material is undoped P3HT, or CuPc or CoPc material.

14 . The TFET of claim 7 , wherein the doped first region is a source region, and wherein the doped second region is a drain region.

15 . A tunneling field effect transistor (TFET), comprising:
a substrate; a doped first region, disposed above the substrate, having p-type organic semiconductor material; a doped second region, disposed above the substrate, having n-type organic semiconductor material; and
a gate stack coupled to the doped source and drain regions.

16 . The TFET of claim 15 , wherein the p-type organic semiconductor material is selected from a group consisting of P3HT, MDMO-PPV, and PEDOT:PSS, CuPc, and CoPc.

17 . The TFET of claim 15 , wherein the n-type organic semiconductor material is one of F16CuPc or SnCl 2 Pc.

18 . The TFET of claim 15 , wherein the TFET is a FinFet, Tri-Gate, or square nano-wire based device.

19 . The TFET of claim 15 further comprises a lightly doped n-type organic semiconductor material coupled to the gate stack, the lightly doped n-type material separating the doped first and second regions from one another, wherein the lightly p-type material is undoped PFHT material.

20 . The TFET of claim 15 further comprises a lightly doped p-type organic semiconductor material coupled to the gate stack, the lightly doped p-type material separating the doped first and second regions from one another, wherein the lightly doped p-type material is undoped PFHT material.

21 - 25 . (canceled)

Assignees

• Intel Corp

Inventors

• Aleksov Aleksandar

Classifications

• H10D12/211 Primary

  Gated diodes · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/08

  using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies · CPC title