Semiconductor device

Patent metadata

Field	Value
Publication number	US-12426313-B2
Application number	US-202017788050-A
Country	US
Kind code	B2
Filing date	Dec 14, 2020
Priority date	Dec 27, 2019
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a CPU and an accelerator,
wherein the accelerator comprises a first memory circuit, a second memory circuit, and an arithmetic circuit,
wherein the first memory circuit comprises a first transistor,
wherein the second memory circuit comprises a second transistor,
wherein each of the first transistor and the second transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the arithmetic circuit comprises a third transistor,
wherein the third transistor comprises a semiconductor layer comprising silicon in a channel formation region,
wherein the CPU comprises a CPU core comprising a flip-flop provided with a backup circuit,
wherein the backup circuit comprises a fourth transistor,
wherein the fourth transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the first transistor and the second transistor are provided in different layers, and
wherein the layer comprising the first transistor and the layer comprising the second transistor are provided over a layer comprising the third transistor.

2. The semiconductor device according to claim 1 ,
wherein the backup circuit is configured to retain data stored in the flip-flop in a state where supply of a power supply voltage is stopped at the time of power gating of the CPU.

3. The semiconductor device according to claim 1 ,
wherein the first memory circuit and the second memory circuit are configured to retain data input to the arithmetic circuit.

4. The semiconductor device according to claim 1 ,
wherein a circuit configuration of the second memory circuit is different from a circuit configuration of the first memory circuit.

5. A semiconductor device comprising:
a CPU and an accelerator,
wherein the accelerator comprises a first memory circuit, a second memory circuit, and an arithmetic circuit,
wherein the first memory circuit comprises a first transistor,
wherein the second memory circuit comprises a second transistor,
wherein each of the first transistor and the second transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the arithmetic circuit comprises a third transistor,
wherein the third transistor comprises a semiconductor layer comprising silicon in a channel formation region,
wherein the first transistor and the second transistor are provided in different layers,
wherein the layer comprising the first transistor is provided over a layer comprising the third transistor,
wherein the layer comprising the second transistor is provided over the layer comprising the first transistor, and
wherein data retention characteristics of the first memory circuit are different from data retention characteristics of the second memory circuit.

6. The semiconductor device according to claim 5 ,
wherein the first memory circuit is configured to retain data input to the arithmetic circuit or data output from the arithmetic circuit.

7. The semiconductor device according to claim 5 ,
wherein an amplitude voltage for driving the first transistor is lower than an amplitude voltage for driving the second transistor.

8. The semiconductor device according to claim 5 ,
wherein a thickness of a gate insulating film of the first transistor is smaller than a thickness of a gate insulating film of the second transistor.

9. The semiconductor device according to claim 5 ,
wherein a circuit configuration of the second memory circuit is different from a circuit configuration of the first memory circuit.

10. The semiconductor device according to claim 1 ,
wherein the arithmetic circuit is configured to perform product-sum operation.

11. The semiconductor device according to claim 1 ,
wherein the metal oxide comprises In, Ga, and Zn.

12. The semiconductor device according to claim 5 ,
wherein the arithmetic circuit is configured to perform product-sum operation.

13. The semiconductor device according to claim 5 ,
wherein the metal oxide comprises In, Ga, and Zn.

Assignees

• Semiconductor Energy Lab

Inventors

• Onuki tatsuya
• Kozuma Munehiro
• Aoki Takeshi
• Matsuzaki Takanori
• Okamoto Yuki
• Oota Masashi
• Nagatsuka Shuhei
• Kunitake Hitoshi
• Yamazaki Shunpei

Classifications

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• G06N3/02

  Neural networks · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B12/00

  Dynamic random access memory [DRAM] devices · CPC title