Memory cell including transistor and capacitor

Patent metadata

Field	Value
Publication number	US-9406348-B2
Application number	US-201414577491-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 26, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A semiconductor storage device capable of performing low-voltage operation, reducing standby current, and decreasing memory size is provided. The semiconductor storage device is a semiconductor device including first to fourth transistors and a capacitor. The first transistor has a function of supplying a first signal to the capacitor. The capacitor has a function of accumulating electric charge based on the first signal. The second transistor has a function of supplying the electric charge based on the first signal to a gate of the third transistor. The third transistor has a function of outputting a first potential to a wiring and a function of supplying the first potential to a gate of the fourth transistor. The fourth transistor has a function of supplying a second potential to the capacitor through the second transistor.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor; and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a first terminal of the capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the first terminal of the capacitor,
wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth wiring, and
wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the third transistor.

2. The semiconductor device according to claim 1 , further comprising a fifth transistor, a sixth transistor, and a seventh transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the third wiring through the fifth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor through the sixth transistor, and
wherein the gate of the fourth transistor is electrically connected to the fourth wiring through the seventh transistor.

3. The semiconductor device according to claim 1 ,
wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor.

4. The semiconductor device according to claim 1 , further comprising an eighth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to the one of the source and the drain of the third transistor, and
wherein the other of the source and the drain of the eighth transistor is electrically connected to the gate of the third transistor.

5. The semiconductor device according to claim 1 , further comprising a ninth transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to one of the source and the drain of the first transistor, and
wherein the other of the source and the drain of the ninth transistor is electrically connected to the gate of the third transistor.

6. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor; and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a first terminal of the capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the first terminal of the capacitor,
wherein the other of the source and the drain of the second transistor is electrically connected to a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the seventh transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a fourth wiring,
wherein one of a source and a drain of the seventh transistor is electrically connected to the fourth wiring, and
wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the third transistor.

7. The semiconductor device according to claim 6 ,
wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor.

8. The semiconductor device according to claim 6 , further comprising an eighth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to the one of the source and the drain of the third transistor, and
wherein the other of the source and the drain of the eighth transistor is electrically connected to the gate of the third transistor.

9. The semiconductor device according to claim 6 , further comprising a ninth transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to one of the source and the drain of the first transistor, and
wherein the other of the source and the drain of the ninth transistor is electrically connected to the gate of the third transistor.

10. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
an eighth transistor; and
a capacitor,
wherein the first transistor is configured to supply a first signal to the capacitor,
wherein the capacitor is configured to hold a potential based on the first signal,
wherein the second transistor is configured to supply the potential based on the first signal to a gate of the third transistor,
wherein the third transistor is configured to output a first potential to a wiring and is configured to supply the first potential to a gate of the fourth transistor,
wherein the fourth transistor is configured to supply a second potential to the capacitor through the second transistor, and
wherein the eighth transistor is configured to supply the first potential to the gate of the third transistor.

11. The semiconductor device according to claim 10 ,
wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor.

12. The semiconductor device according to claim 10 , further comprising a ninth transistor,
wherein the ninth transistor is configured to supply the first signal to the gate of the third transistor.

13. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor; and
a capacitor,
wherein the first transistor is configured to supply a first signal to the capacitor,
wherein the capacitor is configured to hold a potential based on the first signal,
wherein the second transistor is configured to supply the potential based on the first signal to a gate of the third transistor,
wherein the third transistor is configured to supply a first potential to a first wiring through the fourth transistor and is configured to supply the first potential to a gate of the seventh transistor through the fifth transistor,
wherein the sixth transi

Assignees

• Semiconductor Energy Lab

Inventors

• Maehashi Yukio

Classifications

• G11C11/24 Primary

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• G11C2207/2209

  Concurrent read and write · CPC title

• G11C7/1075

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title

• G11C5/06 Primary

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• H01L27/1116

  Electricity · mapped topic