Semiconductor device

Patent metadata

Field	Value
Publication number	US-9437273-B2
Application number	US-201314139248-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 26, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

To provide a semiconductor device that has a novel structure and achieves a higher degree of convenience, the semiconductor device is configured to include a memory cell that stores binary data or multilevel data, and a reading circuit that reads the data stored in the memory cell and transfers the data to the outside. The reading circuit includes a first reading circuit for reading binary data and a second reading circuit for reading multilevel data.

First claim

What is claimed is:

1. A semiconductor device comprising:
a switch;
a bit line electrically connected to a first terminal of the switch;
a word line;
a memory cell electrically connected to the bit line and the word line;
a first comparator electrically connected to a second terminal of the switch;
a second comparator electrically connected to a third terminal of the switch; and
a third comparator electrically connected to the third terminal of the switch,
wherein the memory cell is configured to store binary data or multilevel data,
wherein the binary data is supplied from the bit line to the first comparator through the switch when the binary data is read from the memory cell,
wherein the multilevel data is supplied from the bit line to the second comparator through the switch when the multilevel data is read from the memory cell,
wherein the multilevel data is supplied from the bit line to the third comparator through the switch when the multilevel data is read from the memory cell,
wherein the first comparator is configured to compare a level of a first reference voltage and a voltage corresponding to the binary data read from the memory cell,
wherein the second comparator is configured to compare a level of a second reference voltage and a voltage corresponding to the multilevel data read from the memory cell, and
wherein the third comparator is configured to compare a level of a third reference voltage and the voltage corresponding to the multilevel data read from the memory cell.

2. The semiconductor device according to claim 1 ,
wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and
wherein the power supply voltage is not supplied to the first comparator and is supplied to the second comparator and the third comparator when the multilevel data is read from the memory cell.

3. The semiconductor device according to claim 1 ,
wherein the memory cell comprises a first transistor and a second transistor,
wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,
wherein a first terminal of the second transistor is electrically connected to the bit line, and
wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

4. The semiconductor device according to claim 3 ,
wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and
wherein the power supply voltage is not supplied to the first comparator and is supplied to the second comparator and the third comparator when the multilevel data is read from the memory cell.

5. The semiconductor device according to claim 3 ,
wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and
wherein the power supply voltage is supplied to the first comparator, the second comparator, and the third comparator when the multilevel data is read from the memory cell.

6. A semiconductor device comprising:
a switch;
a bit line electrically connected to a first terminal of the switch;
a word line;
a memory cell electrically connected to the bit line and the word line;
a first comparator electrically connected to a second terminal of the switch;
a second comparator electrically connected to a third terminal of the switch;
a third comparator electrically connected to the third terminal of the switch; and
a writing circuit electrically connected to the bit line,
wherein the memory cell is configured to store binary data or multilevel data,
wherein the binary data is supplied from the bit line to the first comparator through the switch when the binary data is read from the memory cell,
wherein the multilevel data is supplied from the bit line to the second comparator through the switch when the multilevel data is read from the memory cell,
wherein the multilevel data is supplied from the bit line to the third comparator through the switch when the multilevel data is read from the memory cell,
wherein the first comparator is configured to compare a level of a first reference voltage and a voltage corresponding to the binary data read from the memory cell,
wherein the second comparator is configured to compare a level of a second reference voltage and a voltage corresponding to the multilevel data read from the memory cell,
wherein the third comparator is configured to compare a level of a third reference voltage and the voltage corresponding to the multilevel data read from the memory cell,
wherein the writing circuit is configured to output one of a first voltage and a second voltage to the memory cell through the bit line in accordance with the binary data, and
wherein the writing circuit is configured to output one of a third voltage, a fourth voltage, and a fifth voltage to the memory cell through the bit line in accordance with the multilevel data.

7. The semiconductor device according to claim 6 ,
wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and
wherein the power supply voltage is not supplied to the first comparator and is supplied to the second comparator and the third comparator when the multilevel data is read from the memory cell.

8. The semiconductor device according to claim 6 ,
wherein the memory cell comprises a first transistor and a second transistor,
wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,
wherein a first terminal of the second transistor is electrically connected to the bit line, and
wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

9. The semiconductor device according to claim 8 ,
wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and
wherein the power supply voltage is not supplied to the first comparator and is supplied to the second comparator and the third comparator when the multilevel data is read from the memory cell.

10. The semiconductor device according to claim 8 ,
wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and
wherein the power supply voltage is supplied to the first comparator, the second comparator, and the third comparator when the multilevel data is read from the memory cell.

11. A semiconductor device comprising:
a bit line;
a word line;
a memory cell electrically connected to the bit line and the word line;
a first switch electrically connected to the bit line;
a second switch;
a first comparator electrically connected to a first terminal of the first switch and a first terminal of the second switch;
a second comparator electrically connected to a second terminal of the first switch and a second terminal of the second switch;
a third comparator electrically connected to the second terminal of the first switch and the second terminal of the second switch;
a writing circuit electrically connected to the bit line; and
a voltage generator circuit electrically connected to the second switch.

12. The semic

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun

Classifications

• G11C11/5621

  using charge storage in a floating gate · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/405 Primary

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title