Memory device

Patent metadata

Field	Value
Publication number	US-9786350-B2
Application number	US-201414208714-A
Country	US
Kind code	B2
Filing date	Mar 13, 2014
Priority date	Mar 18, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A memory device with a novel structure that is suitable for a register file is provided. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit includes a first logic element and a second logic element each of which is configured to perform logic inversion, a selection circuit, a first switch, a second switch, and a third switch. The second memory circuit includes a first transistor in which a channel formation region is provided in an oxide semiconductor film, a second transistor, and a capacitor to which a potential is supplied through the first transistor.

First claim

What is claimed is:

1. A semiconductor device comprising a memory device, the memory device including:
a first memory circuit comprising:
an inverter;
a clocked inverter;
a first switch;
a second switch;
a third switch; and
a selection circuit, and

a second memory circuit comprising:
a first transistor comprising an oxide semiconductor;
a second transistor; and
a capacitor connected to the first transistor,

wherein one terminal of the first switch is connected to an input terminal of the inverter, an output terminal of the clocked inverter, and one of a source and a drain of the first transistor,
wherein an output terminal of the inverter is connected to a first input terminal of the selection circuit,
wherein an output terminal of the selection circuit is connected to an input terminal of the clocked inverter,
wherein the output terminal of the selection circuit is connected to a first output terminal of the memory device via the second switch,
wherein the output terminal of the selection circuit is connected to a second output terminal of the memory device via the third switch,
wherein one of a source and a drain of the second transistor is connected to a second input terminal of the selection circuit, and
wherein a gate of the second transistor is connected to the other of the source and the drain of the first transistor.

2. The semiconductor device according to claim 1 , wherein the memory device is a register included in a register file.

3. The semiconductor device according to claim 1 ,
wherein the second transistor includes silicon.

4. The semiconductor device according to claim 1 , wherein each of the first switch, the second switch, and the third switch is a transmission gate.

5. The semiconductor device according to claim 1 , wherein the oxide semiconductor contains at least indium and zinc.

6. The semiconductor device according to claim 1 , wherein a signal including a data is input to the other terminal of the first switch.

7. A semiconductor device comprising a memory device, the memory device including:
a first memory circuit comprising:
a NAND logic gate;
a clocked inverter;
a first switch;
a second switch;
a third switch; and
a selection circuit, and

a second memory circuit comprising:
a first transistor;
a second transistor; and
a capacitor connected to the first transistor,

wherein one terminal of the first switch is connected to a first input terminal of the NAND logic gate, an output terminal of the clocked inverter, and one of a source and a drain of the first transistor,
wherein an output terminal of the NAND logic gate is connected to a first input terminal of the selection circuit,
wherein an output terminal of the selection circuit is connected to an input terminal of the clocked inverter,
wherein the output terminal of the selection circuit is connected to a first output terminal of the memory device via the second switch,
wherein the output terminal of the selection circuit is connected to a second output terminal of the memory device via the third switch,
wherein one of a source and a drain of the second transistor is connected to a second input terminal of the selection circuit, and
wherein a gate of the second transistor is connected to the other of the source and the drain of the first transistor.

8. The semiconductor device according to claim 7 , wherein the memory device is a register included in a register file.

9. The semiconductor device according to claim 7 ,
wherein the first transistor comprises an oxide semiconductor, and
wherein the second transistor includes silicon.

10. The semiconductor device according to claim 7 , wherein each of the first switch, the second switch, and the third switch is a transmission gate.

11. The semiconductor device according to claim 9 , wherein the oxide semiconductor contains at least indium and zinc.

12. The semiconductor device according to claim 7 , wherein a signal including a data is input to the other terminal of the first switch.

13. The semiconductor device according to claim 7 , wherein a reset signal is input to a second input terminal of the NAND logic gate.

14. The semiconductor device according to claim 13 ,
wherein the first transistor comprises silicon,
wherein a gate of the first transistor is connected to the second input terminal of the NAND logic gate, and
wherein the first transistor is connected to a third transistor comprising an oxide semiconductor that is included in a third memory circuit.

Assignees

• Semiconductor Energy Lab

Inventors

• Ohmaru Takuro

Classifications

• G11C11/403 Primary

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• G11C2207/007

  Register arrays · CPC title

• G11C14/0054

  in which the volatile element is a SRAM cell · CPC title

• G11C11/24 Primary

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• H01L27/1156

  Electricity · mapped topic