Field programmable gate array utilizing two-terminal non-volatile memory
US-9191000-B2 · Nov 17, 2015 · US
Memory element and programmable logic device
US8934299B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8934299-B2 |
| Application number | US-201313940312-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 12, 2013 |
| Priority date | Jul 18, 2012 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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To provide a memory element where a desired potential can be stored as data without an increase in the number of power source potentials. The memory element stores data in a node which is brought into a floating state by turning off a transistor a channel of which is formed in an oxide semiconductor layer. The potential of a gate of the transistor can be increased by capacitive coupling between the gate and a source of the transistor. With the structure, a desired potential can be stored as data without an increase in the number of power source potentials.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a first wiring configured to supply a high power source potential and a low power source potential; a second wiring configured to supply the high power source potential; a third wiring configured to supply the high power source potential and the low power source potential; a first n-channel transistor, one of a source and a drain of which is electrically connected to the first wiring; a second n-channel transistor,…
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Electricity · mapped topic
Electricity · mapped topic
Physics · mapped topic
- H03K19/17764Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8934299B2 cover?
- To provide a memory element where a desired potential can be stored as data without an increase in the number of power source potentials. The memory element stores data in a node which is brought into a floating state by turning off a transistor a channel of which is formed in an oxide semiconductor layer. The potential of a gate of the transistor can be increased by capacitive coupling between…
- Who is the assignee on this patent?
- Semiconductor Energy Lab
- What technology area does this patent fall under?
- Primary CPC classification H03K19/17764. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).