Programmable logic device and semiconductor device

Patent metadata

Field	Value
Publication number	US-9172369-B2
Application number	US-201414276004-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	May 17, 2013
Publication date	Oct 27, 2015
Grant date	Oct 27, 2015

Abstract

A programmable logic device having low power consumption with operation speed maintained is provided. The programmable logic device includes a first circuit; a second circuit; a first transistor making electrical connection between the first circuit and the second circuit depending on a potential of a gate of the first transistor; a first switch configured to control supply of a signal to a first node; a second switch configured to control supply of the signal to a second node; a second transistor having a gate and one of a source and a drain that are electrically connected to the first node and having the other of the source and the drain that is electrically connected to the second node; and a capacitor that holds a potential of the signal supplied to the first node.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor having a gate, a source, and a drain;
a second transistor having a gate, a source, and a drain, wherein the gate of the second transistor and one of the source and the drain of the second transistor are electrically connected to a first node, and another one of the source and the drain of the second transistor is electrically connected to a second node, and wherein the second node is electrically connected to the gate of the first transistor;
a first switch electrically connected to the first node, wherein the first switch has a first terminal electrically connected to the first node and a second terminal electrically connected to a first wiring;
a second switch electrically connected to the second node, wherein the second switch has a first terminal electrically connected to the second node and a second terminal electrically connected to the first wiring; and
a capacitor electrically connected to the first node.

2. The semiconductor device according to claim 1 ,
wherein the first switch and the second switch are a third transistor and a fourth transistor, respectively, and
wherein each of the second transistor, the third transistor, and the fourth transistor includes a channel formation region in an oxide semiconductor film.

3. The semiconductor device according to claim 2 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

4. The semiconductor device according to claim 1 , wherein the semiconductor device includes a programmable logic device.

5. A programmable logic device comprising:
a first transistor having a gate, a source, and a drain, wherein one of the source and the drain of the first transistor is electrically connected to a first circuit, and another one of the source and the drain of the first transistor is electrically connected to a second circuit;
a second transistor having a gate, a source, and a drain, wherein the gate of the second transistor and one of the source and the drain of the second transistor are electrically connected to a first node, and another one of the source and the drain of the second transistor is electrically connected to a second node, and wherein the second node is electrically connected to the gate of the first transistor;
a first switch having a first terminal electrically connected to the first node and a second terminal electrically connected to a first wiring;
a second switch having a first terminal electrically connected to the second node and a second terminal electrically connected to the first wiring; and
a capacitor having a first electrode electrically connected to the first node.

6. The programmable logic device according to claim 5 ,
wherein the first switch is a third transistor having a gate, a source, and a drain,
wherein one of the source and the drain of the third transistor is electrically connected to the first node, another one of the source and the drain of the third transistor is electrically connected to the first wiring, and the gate of the third transistor is electrically connected to a second wiring,
wherein the second switch is a fourth transistor having a gate, a source, and a drain, and
wherein one of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor through the second node, another one of the source and the drain of the fourth transistor is electrically connected to the first wiring, and the gate of the fourth transistor is electrically connected to the second wiring.

7. The programmable logic device according to claim 5 ,
wherein the first switch and the second switch are a third transistor and a fourth transistor, respectively, and
wherein each of the second transistor, the third transistor, and the fourth transistor includes a channel formation region in an oxide semiconductor film.

8. The programmable logic device according to claim 7 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

9. A programmable logic device comprising:
a first transistor having a gate, a source, and a drain, one of the source and the drain of the first transistor electrically connected to a first circuit, and another one of the source and the drain of the first transistor electrically connected to a second circuit, wherein the first transistor is configured to control electrical connection between the first circuit and the second circuit in accordance with a potential of the gate of the first transistor;
a second transistor having a gate, a source, and a drain, the gate and one of the source and the drain of the second transistor electrically connected to a first node, and another one of the source and the drain of the second transistor electrically connected to a second node;
a first switch configured to control supply of a signal to the first node;
a second switch configured to control supply of the signal to the second node; and
a capacitor configured to hold a potential of the signal supplied to the first node.

10. The programmable logic device according to claim 9 ,
wherein the first switch is a third transistor having a gate, a source, and a drain,
wherein one of the source and the drain of the third transistor is electrically connected to the first node, another one of the source and the drain of the third transistor is electrically connected to a first wiring, and the gate of the third transistor is electrically connected to a second wiring,
wherein the second switch is a fourth transistor having a gate, a source, and a drain, and
wherein one of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor through the second node, another one of the source and the drain of the fourth transistor is electrically connected to the first wiring, and the gate of the fourth transistor is electrically connected to the second wiring.

11. The programmable logic device according to claim 9 ,
wherein the first switch and the second switch are a third transistor and a fourth transistor, respectively, and
wherein each of the second transistor, the third transistor, and the fourth transistor includes a channel formation region in an oxide semiconductor film.

12. The programmable logic device according to claim 11 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

Assignees

• Semiconductor Energy Lab

Inventors

• Okamoto Yuki
• Kurokawa Yoshiyuki

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title