Reducing data backup and recovery periods in processors

Patent metadata

Field	Value
Publication number	US-9372694-B2
Application number	US-201313796063-A
Country	US
Kind code	B2
Filing date	Mar 12, 2013
Priority date	Mar 29, 2012
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A low-power processor that does not easily malfunction is provided. Alternatively, a low-power processor having high processing speed is provided. Alternatively, a method for driving the processor is provided. In power gating, the processor performs part of data backup in parallel with arithmetic processing and performs part of data recovery in parallel with arithmetic processing. Such a driving method prevents a sharp increase in power consumption in a data backup period and a data recovery period and generation of instantaneous voltage drops and inhibits increases of the data backup period and the data recovery period.

First claim

What is claimed is:

1. A processor comprising:
an instruction decoder;
a logic unit including a plurality of logic circuit blocks including a volatile memory block and a nonvolatile memory block;
a backup/recovery controller including a storage storing first reference instruction enumeration and second reference instruction enumeration;
a power controller; and
a flag storage,
wherein the instruction decoder receives an instruction from an outside of the processor and gives an instruction to the logic unit, the backup/recovery controller, and the power controller,
wherein, when enumeration of the instruction from the outside of the processor corresponds to at least part of the first reference instruction enumeration, the backup/recovery controller gives an instruction to back up data from the volatile memory block to the nonvolatile memory block to at least one of the plurality of logic circuit blocks in accordance with the first reference instruction enumeration,
wherein the backup/recovery controller receives an instruction from the instruction decoder and gives an instruction to recover data from the nonvolatile memory block to the volatile memory block to at least one of the plurality of logic circuit blocks in accordance with the second reference instruction enumeration,
wherein one of the logic circuit blocks in the logic unit receives an instruction from the backup/recovery controller, and performs data backup or data recovery between the volatile memory block and the nonvolatile memory block,
wherein another one of the logic circuit blocks in the logic unit concurrently receives an instruction from the instruction decoder and performs arithmetic processing using data stored in the volatile memory block,
wherein a data backed up flag or a data recovered flag is written to the flag storage by the backup/recovery controller, and
wherein the power controller receives an instruction from the instruction decoder or the backup/recovery controller and powers on or off the logic unit.

2. The processor according to claim 1 ,
wherein the data backup performed at the time of stop of the logic unit is divided into primary backup in which data is backed up from the volatile memory block to the nonvolatile memory block in one of the logic circuit blocks in the logic unit before an instruction to stop the logic unit and another one of the logic circuit blocks in the logic unit concurrently performs arithmetic processing, and secondary backup in which data is backed up from the volatile memory block to the nonvolatile memory block in another one of the logic circuit blocks in the logic unit after the instruction to stop the logic unit, and
wherein the data recovery performed at the time of start of the logic unit is divided into primary recovery in which data is recovered from the nonvolatile memory block to the volatile memory block in one of the logic circuit blocks in the logic unit in accordance with an instruction to start the logic unit, and secondary recovery in which data is recovered from the nonvolatile memory block to the volatile memory block in another one of the logic circuit blocks in the logic unit after completion of the primary recovery and one of the logic circuit blocks in the logic unit concurrently performs arithmetic processing.

3. The processor according to claim 2 ,
wherein, in the primary backup, when the enumeration of the instruction from the outside of the processor corresponds to at least part of the first reference instruction enumeration, the backup/recovery controller gives an instruction to back up data from the volatile memory block to the nonvolatile memory block to at least one of the logic circuit blocks in the logic unit,
wherein one of the logic circuit blocks in the logic unit receives the instruction from the backup/recovery controller and backs up data from the volatile memory block to the nonvolatile memory block,
wherein another one of the logic circuit blocks in the logic unit concurrently performs arithmetic processing,
wherein the backup/recovery controller writes a backed up flag of one of the logic circuit blocks in the logic unit to the flag storage in accordance with backup of the data in one of the logic circuit blocks in the logic unit,
wherein, in the secondary backup, the instruction decoder receives an instruction to stop the logic unit from the outside of the processor and gives an instruction to back up data in the logic unit to the backup/recovery controller,
wherein the backup/recovery controller gives an instruction to back up data from the volatile memory block to the nonvolatile memory block to another one of the logic circuit blocks in the logic unit in accordance with the backed up flag,
wherein another one of the logic circuit blocks in the logic unit backs up data from the volatile memory block to the nonvolatile memory block,
wherein the backup/recovery controller gives an instruction to power off at least the logic unit to the power controller after completion of backup of the data in another one of the logic circuit blocks in the logic unit, and
wherein the power controller powers off at least the logic unit.

4. The processor according to claim 3 , wherein, in the primary backup, in the case where another data is written to one of the logic circuit blocks in the logic unit from which the data is backed up, the backed up flag of the logic circuit block written to the flag storage is erased.

5. The processor according to claim 3 , wherein, in the primary backup, one of the logic circuit blocks in the logic unit is divided into a plurality of blocks and the primary backup is performed more than once.

6. The processor according to claim 1 ,
wherein, in the primary backup, the instruction decoder receives an instruction to start the logic unit from the outside of the processor, gives an instruction to power on the logic unit to the power controller, and gives an instruction to recover data in the logic unit to the backup/recovery controller,
wherein the power controller receives the instruction from the instruction decoder and powers on at least the logic unit,
wherein the backup/recovery controller receives the instruction from the instruction decoder and gives an instruction to recover data from the nonvolatile memory block to the volatile memory block to one of the logic circuit blocks in the logic unit in accordance with the second reference instruction enumeration,
wherein one of the logic circuit blocks in the logic unit recovers data from the nonvolatile memory block to the volatile memory block,
wherein the backup/recovery controller writes a recovered flag of one of the logic circuit blocks in the logic unit to the flag storage in accordance with recovery of the data in one of the logic circuit blocks in the logic unit,
wherein a data recovery completion signal of one of the logic circuit blocks in the logic unit is transmitted to the instruction decoder after completion of recovery of the data in one of the logic circuit blocks in the logic unit,
wherein, in the secondary recovery, the instruction decoder receives the data recovery completion signal and gives an instruction to perform arithmetic processing to one of the logic circuit blocks in the logic unit,
wherein the backup/recovery controller gives an instruction to recover data from the nonvolatile memory block to the volatile memory block to another one of the logic circuit blocks in the logic unit,
wherein another one of the logic circuit blocks in the logic unit recovers data from the nonvolatile memory block to the volatile memory block,
wherein one of the logic circuit blocks in the logic unit concurrently performs arithmetic processing in accordance with the instruction from the instruction decoder, and
wherein the backup/recovery contr

Assignees

• Semiconductor Energy Lab

Inventors

• Yoneda Seiichi

Classifications

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30141

  Implementation provisions of register files, e.g. ports · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• Y02B60/32

  Cross-Sectional Technologies · mapped topic

• G11C5/00

  Details of stores covered by group G11C11/00 · CPC title