Self-aligned scheme for semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-12387977-B2
Application number	US-202318447889-A
Country	US
Kind code	B2
Filing date	Aug 10, 2023
Priority date	Sep 26, 2019
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

First claim

What is claimed is:

1. A device comprising:
a first dielectric layer disposed on a substrate;
a first conductive feature disposed in the first dielectric layer, wherein a top surface of the first conductive feature is recessed relative to the top surface of the first dielectric layer;
a first barrier layer disposed in the first dielectric layer between the first conductive feature and the first dielectric layer, the first barrier layer having a sidewall surface interfacing with the first conductive feature;
a second dielectric layer disposed directly on the top surface of the first dielectric layer; and
an etch stop layer extending form over the second dielectric layer to the sidewall surface of the first barrier layer such that the etch stop layer interfaces with the sidewall surface of the first barrier layer.

2. The device of claim 1 , further comprising:
a third dielectric layer disposed on the etch stop layer; and
a second conductive feature extending through the third dielectric layer, the second dielectric layer and the etch stop layer, wherein the second conductive feature is electrically coupled to the first conductive feature.

3. The device of claim 2 , wherein the second conductive feature further extends within the first dielectric layer to a depth below the top surface of the first dielectric layer.

4. The device of claim 2 , further comprising a second barrier layer disposed around the second conductive feature and extending through the third dielectric layer, the second dielectric layer, the etch stop layer and to the first conductive feature such that the second barrier layer interfaces with the first conductive feature and the first barrier layer.

5. The device of claim 4 , wherein the second dielectric layer has a top surface facing away from the substrate, a bottom surface facing the substrate and a side surface extending from the bottom surface to the top surface of the second dielectric layer,
wherein the second barrier layer interfaces with the side surface and top surface of the second dielectric layer, and
wherein the first dielectric layer interfaces with the bottom surface of the second dielectric layer.

6. The device of claim 5 , wherein the etch stop layer interfaces with the top surface of the second dielectric layer.

7. The device of claim 1 , further comprising a cobalt-containing layer disposed directly on the top surface of the first conductive feature such that the cobalt-containing layer interfaces with the top surface of the first conductive feature.

8. The device of claim 7 , wherein the cobalt-containing layer extends to and interfaces with the sidewall surface of the first barrier layer.

9. A device comprising:
a first dielectric layer disposed on a substrate;
a first conductive component at least partially embedded in the first dielectric layer;
a metal-containing layer disposed directly on the first conductive component;
a second dielectric layer disposed on the first dielectric layer, wherein a top surface of the metal-containing layer is recessed relative to a top surface of the second dielectric layer;
a first etch stop layer disposed directly on the second dielectric layer and the top surface of the metal-containing layer such that the first etch stop layer physically contacts the second dielectric layer and the top surface of the metal-containing layer;
a second etch stop layer disposed directly on the first etch stop layer such that the second etch stop layer physically contacts the first etch stop layer; and
a second conductive component extending through and physically contacting the second etch stop layer, the first etch stop layer, the metal-containing layer and the first conductive component.

10. The device of claim 9 , wherein the second conductive component physically contacts the second dielectric layer.

11. The device of claim 9 , further comprising a third etch stop layer disposed directly on the second etch stop layer such that the third etch stop layer physically contacts the second etch stop layer, and
wherein the second conductive component further extends through and physically contacts the third etch stop layer.

12. The device of claim 9 , wherein the first conductive component includes:
a first conductive feature; and
a first barrier layer disposed along an outer perimeter of the first conductive feature, and
wherein the second conductive component includes:
a second conductive feature; and
a second barrier layer disposed along an outer perimeter of the second conductive feature.

13. The device of claim 12 , wherein the metal-containing layer physically contacts the first barrier layer and the first conductive feature, and
wherein the second barrier layer physically contacts the second etch stop layer, the first etch stop layer, the first barrier layer and the first conductive feature.

14. The device of claim 9 , wherein the second dielectric layer physically contacts the first dielectric layer.

15. The device of claim 9 , wherein the first and second etch stop layers extend within the first dielectric layer to a depth below a top surface the first dielectric layer.

16. A method comprising:
providing a first conductive component disposed in a first dielectric layer over a substrate;
forming a metal-containing layer on the first conductive component such that the first conductive component is covered by the metal-containing layer;
forming a self-assembling monolayer on the metal-containing layer;
after the forming of the self-assembling monolayer on the metal-containing layer, forming a second dielectric layer on the first dielectric layer, wherein at least a portion of a top surface of the self-assembly monolayer is exposed after the forming of the second dielectric layer on the first dielectric layer;
after forming the second dielectric layer, removing at least a portion of the self-assembly monolayer to expose the metal-containing layer; and
forming a second conductive component on the exposed metal-containing layer.

17. The method of claim 16 , wherein the first conductive component includes:
a first conductive feature; and
a first barrier layer disposed along an outer perimeter of the first conductive feature.

18. The method of claim 17 , further comprising recessing the first conductive feature prior to the forming of the metal-containing layer on the first conductive component, wherein the first barrier layer extends to a greater height above the substrate than the first conductive feature after the recessing of the first conductive feature.

19. The method of claim 16 , wherein the removing of at least the portion of the self-assembly monolayer to expose the metal-containing layer includes applying a hydrogen treatment process.

20. The method of claim 16 , wherein the removing of at least the portion of the self-assembly monolayer to expose the metal-containing layer includes applying a nitrogen treatment process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsueh Hsiu-Wen
• Wu cai-ling
• Tseng Ya-Ching
• Chen Chii-Ping
• Yang Neng-Jye

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title