Back end of line (BEOL) time dependent dielectric breakdown (TDDB) mitigation within a vertical interconnect access (VIA) level of an integrated circuit (IC) device

Patent metadata

Field	Value
Publication number	US-10998263-B2
Application number	US-201916440050-A
Country	US
Kind code	B2
Filing date	Jun 13, 2019
Priority date	Jun 13, 2019
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.

First claim

The invention claimed is:

1. An integrated circuit (IC) device fabrication method comprising:
forming a first lower wiring line and a second wiring line within a lower wiring layer;
forming a diffusion barrier layer upon the lower wiring layer;
forming an upper wiring layer upon the diffusion barrier layer;
forming an upper wiring line trench by etching away a first portion of the upper wiring layer;
forming a chamfered vertical interconnect access (VIA) trench by etching away a second portion of the upper wiring layer stopping upon an upper surface of the diffusion barrier layer and subsequently etching away a portion of the diffusion barrier layer stopping upon an internal angled plane of the diffusion barrier layer, the chamfered VIA trench comprising a vertical sidewall of the upper wiring layer and a chamfered surface of the diffusion barrier layer connected to the vertical sidewall, the chamfered VIA trench exposing at least a portion of the first lower wiring line and a portion of the lower wiring layer between the first wiring line and the second wiring line there below;
selectively forming a monolayer solely upon the exposed portion of the first lower wiring line within the chamfered VIA trench;
forming a dielectric film layer upon the vertical sidewall, upon the chamfered surface within the chamfered VIA trench, and upon the portion of the lower wiring layer between the first wiring line and the second wiring line;
removing the monolayer from the chamfered VIA trench to re-expose the portion of the first lower wiring line while retaining the dielectric film layer upon the vertical sidewall, upon the chamfered surface within the VIA trench, and upon the portion of the lower wiring layer between the first wiring line and the second wiring line, wherein removing the monolayer from the chamfered VIA trench comprises forming a sacrificial plug upon the dielectric film layer and upon the monolayer within the chamfered VIA trench and simultaneously removing the sacrificial plug and monolayer from the chamfered VIA trench;
forming a chamfered VIA within the chamfered VIA trench upon the re-exposed portion of the first lower wiring line and upon the portion of the lower wiring layer between the first wiring line and the second wiring line.

2. The fabrication method of claim 1 , wherein the chamfered VIA comprises a vertical sidewall, a contact surface connected to the re-exposed portion of the first lower wiring line and connected to the portion of the lower wiring layer between the first wiring line and the second wiring line, and a chamfer that connects the vertical sidewall with the contact surface.

3. The fabrication method of claim 1 , further comprising:
forming an upper wiring line within the upper wiring line trench, wherein the chamfered VIA connects the first lower wiring line and the upper wiring line.

4. The fabrication method of claim 1 , wherein the chamfered VIA is offset from the first lower wiring line.

5. The fabrication method of claim 1 , wherein the chamfered VIA is in line with the first lower wiring line.

6. The fabrication method of claim 1 , wherein the monolayer is a one molecule thick layer.

7. An integrated circuit (IC) device fabrication method comprising:
forming a first lower wiring line and a second wiring line within a lower wiring layer;
forming a diffusion barrier layer upon the lower wiring layer;
forming an upper wiring layer upon the diffusion barrier layer;
forming an upper wiring line trench by etching away a first portion of the upper wiring layer;
forming a chamfered vertical interconnect access (VIA) trench by etching away a second portion of the upper wiring layer stopping upon an upper surface of the diffusion barrier layer and subsequently etching away a portion of the diffusion barrier layer stopping upon an internal angled plane of the diffusion barrier layer, the chamfered VIA trench comprising a vertical sidewall of the upper wiring layer and a chamfered surface of the diffusion barrier layer connected to the vertical sidewall, the chamfered VIA trench exposing at least a portion of the first lower wiring line and a portion of the lower wiring layer between the first wiring line and the second wiring line there below;
selectively forming a monolayer solely upon the exposed portion of the first lower wiring line within the chamfered VIA trench;
forming a dielectric film layer upon the vertical sidewall and the chamfered surface within the chamfered VIA trench and within the upper wiring line trench;
removing monolayer from the VIA trench to re-expose the portion of the lower wiring line retaining the dielectric film layer upon the vertical sidewall, upon the chamfered surface within the VIA trench, and upon the portion of the lower wiring layer between the first wiring line and the second wiring line, wherein removing the monolayer from the chamfered VIA trench comprises forming a sacrificial plug upon the dielectric film layer and upon the monolayer within the chamfered VIA trench and simultaneously removing the sacrificial plug and monolayer from the chamfered VIA trench; and
forming a chamfered VIA within the chamfered VIA trench upon the re-exposed portion of the first lower wiring line and upon the portion of the lower wiring layer between the first wiring line and the second wiring line.

8. The fabrication method of claim 7 , wherein the chamfered VIA comprises a vertical sidewall, a contact surface connected to the re-exposed portion of the first lower wiring line and connected to the portion of the lower wiring layer between the first wiring line and the second wiring line, and a chamfer that connects the vertical sidewall with the contact surface.

9. The fabrication method of claim 7 , further comprising:
forming an upper wiring line upon the dielectric film within the upper wiring line trench, wherein the chamfered VIA connects the first lower wiring line and the upper wiring line.

10. The fabrication method of claim 7 , wherein the chamfered VIA is offset from the first lower wiring line.

11. The fabrication method of claim 7 , wherein the chamfered VIA is in line with the first lower wiring line.

12. The fabrication method of claim 7 , wherein the monolayer is a one molecule thick layer.

Assignees

• IBM

Inventors

• Liang Jim Shih-Chun
• Lustig Naftali E
• Li Baozhen
• Lu Ning

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/082 Primary

  the openings being tapered via holes · CPC title

• H10W20/076

  in via holes or trenches · CPC title