Semiconductor structure having through substrate via and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12374602-B2
Application number	US-202217727820-A
Country	US
Kind code	B2
Filing date	Apr 25, 2022
Priority date	Apr 25, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a dielectric layer;
a conductive pad embedded in the dielectric layer;
a semiconductor substrate disposed on the dielectric layer, the semiconductor substrate comprising a via opening with a notch in proximity to the dielectric layer;
a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad; and
a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate, and a sidewall of the dielectric liner facing the TSV being aligned with an inner sidewall of the dielectric layer facing the TSV.

2. The semiconductor structure of claim 1 , wherein a cross section of the notch has a concave curved shape facing the TSV.

3. The semiconductor structure of claim 1 , wherein a lower portion of the dielectric liner filling the notch is an annular ring encircling the TSV in a top view.

4. The semiconductor structure of claim 1 , wherein the via opening of the semiconductor substrate comprises an upper region and a lower region connected to the upper region, the notch is at the lower region, and a maximum width of the upper region is less than a maximum width of the lower region.

5. The semiconductor structure of claim 4 , wherein an opening width of the upper region of the via opening of the semiconductor substrate gradually decreases toward the lower region of the via opening of the semiconductor substrate.

6. The semiconductor structure of claim 1 , wherein lateral surfaces of the dielectric liner and the dielectric layer are smoother than an inner sidewall of the semiconductor substrate defining the via opening.

7. The semiconductor structure of claim 1 , wherein the TSV comprises:
a diffusion barrier layer being in direct contact with the dielectric liner and the dielectric layer;
a seed layer overlying the diffusion barrier layer; and
a conductive material layer filling the via opening of the semiconductor substrate.

8. The semiconductor structure of claim 7 , wherein a combined thickness of the diffusion barrier layer and the seed layer is less than a maximum thickness of a portion of the dielectric liner filling the notch.

9. A semiconductor device, comprising:
a first tier comprising:
a first semiconductor substrate comprising an upper inner sidewall and a lower inner sidewall connected to the upper inner sidewall;
a first dielectric layer underlying the first semiconductor substrate;
a first conductive pattern embedded in the first dielectric layer;
a dielectric liner disposed on the upper inner sidewall and the lower inner sidewall of the first semiconductor substrate, wherein an upper portion of the dielectric liner overlying the upper inner sidewall is thinner than a lower portion of the dielectric liner overlying the lower inner sidewall;
a through substrate via (TSV) comprising an upper portion laterally covered by the dielectric liner and a lower portion laterally covered by the first dielectric layer and connected to the first conductive pattern; and
a first bonding structure underlying the first dielectric layer and connected to the first conductive pattern; and

a second tier disposed below the first tier, wherein the second tier comprises a second bonding structure fused to the first bonding structure.

10. The semiconductor device of claim 9 , wherein the lower inner sidewall of the first semiconductor substrate has a cross sectional profile recessed toward the TSV.

11. The semiconductor device of claim 9 , wherein a lateral surface of the dielectric liner connected to the TSV is substantially leveled with an inner sidewall of the first dielectric layer connected to the TSV.

12. The semiconductor device of claim 9 , wherein a sidewall and a bottom surface of the lower portion of the TSV are in direct with the dielectric layer and the first conductive pattern, respectively.

13. The semiconductor device of claim 9 , wherein the second tier further comprises:
a second semiconductor substrate underlying the second bonding structure;
a second dielectric layer between the second semiconductor substrate and the second bonding structure; and
a second conductive pattern embedded in the second dielectric layer.

14. The semiconductor device of claim 9 , wherein a bonding interface of the first tier and the second tier is substantially flat and comprises metal-to-metal bonds and dielectric-to-dielectric bonds.

15. A manufacturing method of a semiconductor structure, comprising:
forming a via opening to penetrate through a semiconductor substrate overlying the dielectric material layer, wherein the via opening comprises an upper region and a lower region connected to the upper region, and a notch of the lower region recessed into an inner sidewall of the semiconductor substrate;
forming a dielectric liner material in the via opening to laterally cover the semiconductor substrate and overlay the dielectric material layer;
extending the via opening by removing portions of the dielectric liner material and the dielectric material layer to accessibly reveal a conductive pad embedded in the dielectric material layer; and
forming a through substrate via (TSV) in the via opening to land on the conductive pad, wherein forming the TSV comprises:
forming the TSV on a first sidewall of the dielectric liner material, a second sidewall of the dielectric material layer and a top surface of the conductive pad, wherein the first sidewall of the dielectric liner material is aligned with the second sidewall of the dielectric material layer.

16. The manufacturing method of claim 15 , wherein extending the via opening comprises:
performing a dry etching process to remove a portion of the dielectric liner material overlying the dielectric material layer and a portion of the dielectric material layer underlying the portion of the dielectric liner material; and
performing a wet etching process to remove a remaining portion of the dielectric material layer overlying the conductive pad to accessibly reveal the conductive pad.

17. The manufacturing method of claim 15 , wherein extending the via opening comprises:
performing a dry etching process to remove a portion of the dielectric liner material overlying the dielectric material layer and a portion of the dielectric material layer underlying the portion of the dielectric liner material until the conductive pad is accessibly revealed.

18. The manufacturing method of claim 15 , wherein forming the via opening comprises:
performing a dry etching process on the semiconductor substrate, wherein the via opening stops at a top surface of the dielectric material layer.

19. The semiconductor device of claim 9 , wherein the first bonding structure includes a bonding dielectric layer and a bonding connector embedded in the bonding dielectric layer, wherein the bonding connector includes a via portion connected to the first conductive pattern and a pad portion connected with the via portion.

20. The manufacturing method of claim 15 , wherein the dielectric liner material is formed to have a horizontal portion of the dielectric liner material overlying the dielectric material layer being thicker than a upper portion of the dielectric liner material laterally covering the semiconductor substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Wei-Ming
• Lin Yu-Hung
• Lin Yu-Hsiao
• Tai Shih-Peng
• Yee Kuo-Chung

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title