Memory devices having signal routing structures at bonding interfaces
US-2024404976-A1 · Dec 5, 2024 · US
Direct bonding of chips, wafers or substrates
Direct bonding of chips, wafers or substrates · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W80/00 |
| Official title | Direct bonding of chips, wafers or substrates |
| Display label | Direct bonding of chips, wafers or substrates |
| Total patents | 3,785 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2015 | 17 |
| 2016 | 26 |
| 2017 | 42 |
| 2018 | 58 |
| 2019 | 84 |
| 2020 | 184 |
| 2021 | 425 |
| 2022 | 643 |
| 2023 | 809 |
| 2024 | 740 |
| 2025 | 632 |
| 2026 | 125 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor memory device and manufacturing method of semiconductor memory device
US-12144179-B2 · Nov 12, 2024 · US
Microelectronic assemblies with inductors in direct bonding regions
US-2024355768-A1 · Oct 24, 2024 · US
Clock tree routing in a chip stack
US-2024103562-A1 · Mar 28, 2024 · US
Semiconductor storage device
US-2024107765-A1 · Mar 28, 2024 · US
3d layout and organization for enhancement of modern memory systems
US-2024088099-A1 · Mar 14, 2024 · US
Semiconductor package and manufacturing method thereof
US-2024063160-A1 · Feb 22, 2024 · US
Semiconductor package
US-11862613-B2 · Jan 2, 2024 · US
Advanced through substrate via metallization in three dimensional semiconductor integration
US-2017345738-A1 · Nov 30, 2017 · US
Bumpless build-up layer package with pre-stacked microelectronic devices
US-9831213-B2 · Nov 28, 2017 · US
Semiconductor device, manufacturing method thereof, and electronic apparatus
US-9812490-B2 · Nov 7, 2017 · US
Buffer layer(s) on a stacked structure having a via
US-9793243-B2 · Oct 17, 2017 · US
Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US-9754923-B1 · Sep 5, 2017 · US
Integrated circuit package with embedded passive structures
US-9673173-B1 · Jun 6, 2017 · US
Semiconductor memory device with electrode connecting to circuit chip through memory array chip
US-9558945-B2 · Jan 31, 2017 · US
Trap rich layer with through-silicon-vias in semiconductor devices
US-9558951-B2 · Jan 31, 2017 · US
3D Chip-On-Wafer-On-Substrate Structure With Via Last Process
US-2017005027-A1 · Jan 5, 2017 · US
Wafer Bonding Process and Structure
US-2016358882-A1 · Dec 8, 2016 · US
Vertically integrated wafers with thermal dissipation
US-9508685-B2 · Nov 29, 2016 · US
Bumpless build-up layer package with pre-stacked microelectronic devices
US-2016276317-A1 · Sep 22, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W80/00?
- CPC H10W80/00 is the Cooperative Patent Classification code for “Direct bonding of chips, wafers or substrates.”
- How many patents are filed under CPC H10W80/00 (Direct bonding of chips, wafers or substrates)?
- Our database includes 3,785 publications tagged with this CPC code.
- Is patent activity under CPC H10W80/00 growing?
- Publication counts under this code: 740 in 2024 vs 632 in 2025 (latest complete years).