Package formation methods including coupling a molded routing layer to an integrated routing layer
US-2024355697-A1 · Oct 24, 2024 · US
Structure and method for 3D IC package
US8993380B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993380-B2 |
| Application number | US-201313791305-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 8, 2013 |
| Priority date | Mar 8, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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- Title
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Abstract
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Provided is a chip package structure and a method for forming the chip package. The method includes bonding a plurality of first dies on a carrier, encapsulating in a first molding compound the first dies on the carrier, coupling a plurality of second dies on the first dies using conductive elements, adding an underfill between the second dies and the first dies surrounding the conductive elements, and encapsulating in a second molding compound the second dies and the underfill. The chip package comprises a chip encapsulated in a molding compound, and a larger chip coupled to the first chip via conductive elements, wherein the conductive elements are encapsulated in an underfill between the chip and the larger chip without an interposer, and wherein the larger chip and the underfill are encapsulated in a second molding compound in contact with the molding compound.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a chip package comprising: bonding a plurality of first dies on a carrier; encapsulating in a first molding compound the first dies on the carrier; coupling a plurality of second dies on the first dies using conductive elements; adding an underfill between the second dies and the first dies, the underfill surrounding the conductive elements; encapsulating in a second molding compound the second dies and the underfill; and de-bon…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8993380B2 cover?
- Provided is a chip package structure and a method for forming the chip package. The method includes bonding a plurality of first dies on a carrier, encapsulating in a first molding compound the first dies on the carrier, coupling a plurality of second dies on the first dies using conductive elements, adding an underfill between the second dies and the first dies surrounding the conductive eleme…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W74/129. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).