Discrete polymer in fan-out packages

Patent metadata

Field	Value
Publication number	US-9666502-B2
Application number	US-201514690081-A
Country	US
Kind code	B2
Filing date	Apr 17, 2015
Priority date	Apr 17, 2015
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.

First claim

What is clamed is:

1. A package comprising:
a first molding material;
a lower-level device die in the first molding material;
a first dielectric layer over the lower-level device die and the first molding material;
a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die;
an upper-level device die over the first dielectric layer;
a second molding material molding the upper-level device die therein, wherein a bottom surface of a portion of the second molding material contacts a top surface of the first molding material; and
a second dielectric layer over and in contact with both the upper-level device die and the second molding material.

2. The package of claim 1 , wherein the portion of the second molding material forms a full ring encircling the first dielectric layer.

3. The package of claim 1 , wherein the first molding material and the second molding material form a distinguishable interface.

4. The package of claim 1 ,
wherein an edge of the second dielectric layer is parallel to an edge of the package, and is recessed more toward a center of the package than the edge of the package.

5. The package of claim 4 further comprising a third molding material comprising:
a ring portion encircling the second dielectric layer, wherein the ring portion contacts a top surface of the second molding material.

6. The package of claim 5 , wherein the second molding material and the ring portion of the third molding material form a distinguishable interface.

7. The package of claim 5 , wherein the ring portion of the third molding material further comprises a portion coplanar with and encircling the second molding material.

8. The package of claim 1 further comprising a through-via penetrating through the second molding material, wherein the through-via electrically couples the lower-level device die to the upper-level device die.

9. The package of claim 1 further comprising:
a first die attach film overlapped by, and attached to a back surface of, the lower-level device die; and
a second die attach film overlapped by, and attached to a back surface of, the upper-level device die.

10. The package of claim 1 , wherein the second dielectric layer comprises a polymer, with the polymer in physical contact with both the upper-level device die and the second molding material.

11. A package comprising:
a first molding material;
a lower-level device die in the first molding material;
a first polymer layer over the lower-level device die and the first molding material;
a first plurality of redistribution lines extending into the first polymer layer to electrically couple to the lower-level device die;
an upper-level device die over the first polymer layer;
a second molding material molding the upper-level device die therein, wherein a first edge of the first molding material and a second edge of the second molding material are in a same plane to form an edge of the package, and wherein a portion of the second molding material comprises the second edge and a third edge opposite to each other, with the third edge contacting the first polymer layer, and the portion of the second molding material forms a full ring encircling, and contacting respective edges of, the first polymer layer; and
a through-via in the second molding material, wherein the through-via and one of the first plurality of redistribution lines electrically couple the lower-level device die to the upper-level device die.

12. The package of claim 11 , wherein a bottom surface of the portion of the second molding material contacts a top surface of the first molding material to form an interface.

13. The package of claim 12 , wherein the interface is coplanar with a top surface of the lower-level device die.

14. The package of claim 11 further comprising:
a second polymer layer over the upper-level device die and the second molding material;
a second plurality of redistribution lines extending into the second polymer layer to electrically couple to the upper-level device die; and
a third molding material comprising a first portion over the second polymer layer, and a second portion coplanar with and encircling the second polymer layer.

15. The package of claim 14 , wherein the third molding material comprises a portion extending to a same level as the second molding material.

16. A package comprising:
a first encapsulating material;
a lower-level device die encapsulated in the first encapsulating material;
a first plurality of dielectric layers over the lower-level device die and the first encapsulating material, wherein first plurality of dielectric layers extends laterally beyond edges of the lower-level device die;
an upper-level device die over the first plurality of dielectric layers;
a second encapsulating material encapsulating the upper-level device die therein, wherein a bottom surface of a portion of the second encapsulating material contacts a top surface of the first encapsulating material, and inner edges of the second encapsulating material contact outer edges of the first plurality of dielectric layers;
a second plurality of dielectric layers over the upper-level device die and the second encapsulating material, wherein the second plurality of dielectric layers extends laterally beyond edges of the upper-level device die; and
a third encapsulating material over the second encapsulating material, wherein a portion of the third encapsulating material is at a same level as, and contacting the edges of, the second plurality of dielectric layers.

17. The package of claim 16 , wherein the first encapsulating material and the second encapsulating material form a distinguishable interface.

18. The package of claim 16 , wherein the third encapsulating material comprises a first portion over the second encapsulating material, and a second portion lower than a top surface of the second encapsulating material.

19. The package of claim 16 , wherein a bottom surface of a portion of the third encapsulating material and a top surface of the second encapsulating material form a distinguishable interface.

20. The package of claim 16 further comprising an adhesive film having a top surface in contact with a bottom surface of the upper-level device die, and a bottom surface in contact with a top dielectric layer in the first plurality of dielectric layers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei
• Chen Jie

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title