Dummy structure for chip-on-wafer-on-substrate

Patent metadata

Field	Value
Publication number	US-9425126-B2
Application number	US-201414289819-A
Country	US
Kind code	B2
Filing date	May 29, 2014
Priority date	May 29, 2014
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.

First claim

What is claimed is:

1. An apparatus, comprising:
a substrate;
a dielectric layer disposed over the substrate;
a plurality of metal pads disposed in the dielectric layer;
a plurality of through-silicon-vias (TSVs) extending into the substrate, wherein each of the plurality of TSVs is located below a corresponding one of the plurality of metal pads;
a plurality of metal lines disposed in the dielectric layer;
a plurality of first dummy structures disposed in the dielectric layer, wherein each of the plurality of first dummy structures has a first width that is at least about three times greater than a second width of each of the plurality of metal lines; and
a plurality of second dummy structures disposed in the dielectric layer, wherein each of the plurality of second dummy structures has a third width that is at least about five times greater than the second width of each of the plurality of metal lines.

2. The apparatus of claim 1 wherein each of the plurality of TSVs is disposed substantially centered below the corresponding one of the plurality of metal pads.

3. The apparatus of claim 1 wherein an aspect ratio of each of the plurality of TSVs is not less than about 4:1.

4. The apparatus of claim 1 wherein a diameter of each of the plurality of TSVs is not more than about fifteen microns.

5. The apparatus of claim 1 wherein the second width of each of the plurality of metal lines ranges between about 0.1 microns and about 1.0 microns.

6. The apparatus of claim 1 wherein a distance between outer edges of adjacent ones of the plurality of first dummy structures ranges between about 100% and about 250% of a distance between outer edges of adjacent ones of the plurality of metal lines.

7. The apparatus of claim 1 wherein a distance between outer edges of adjacent ones of the plurality of second dummy structures ranges between about 100% and about 250% of a distance between outer edges of adjacent ones of the plurality of metal lines.

8. The apparatus of claim 1 wherein:
a distance between outer edges of adjacent ones of the plurality of first dummy structures ranges between about 100% and about 250% of the distance between outer edges of adjacent ones of the plurality of metal lines; and
a distance between outer edges of adjacent ones of the plurality of second dummy structures ranges between about 100% and about 250% of the distance between outer edges of adjacent ones of the plurality of metal lines.

9. The apparatus of claim 1 wherein each of the plurality of TSVs, each of the plurality of metal pads, each of the plurality of metal lines, each of the plurality of first dummy structures, and each of the plurality of second dummy structures have substantially similar thicknesses.

10. The apparatus of claim 9 wherein each of the plurality of TSVs, each of the plurality of metal pads, each of the plurality of metal lines, each of the plurality of first dummy structures, and each of the plurality of second dummy structures have substantially similar compositions.

11. The apparatus of claim 1 wherein each of the plurality of TSVs, each of the plurality of metal pads, each of the plurality of metal lines, each of the plurality of first dummy structures, and each of the plurality of second dummy structures have substantially similar compositions.

12. An apparatus, comprising:
a substrate;
a dielectric layer disposed on the substrate;
a metal pad disposed in the dielectric layer;
a through-silicon-via (TSV) in the substrate, wherein the TSV is located below the metal pad;
a metal line disposed in the dielectric layer;
a first dummy structure disposed in the dielectric layer, wherein the first dummy structure has a first width that is at least about three times greater than a second width of the metal line; and
a second dummy structure disposed in the dielectric layer, wherein the second dummy structure has a third width that is at least about five times greater than the second width of the metal line.

13. The apparatus of claim 12 wherein the second width of the metal line ranges between about 0.1 microns and about 1.0 microns.

14. The apparatus of claim 12 wherein:
the metal line is a first metal line;
the first dummy structure is a first first dummy structure;
the second dummy structure is a first second dummy structure;
the apparatus further comprises:
a second metal line;
a second first dummy structure; and
a second second dummy structure;

a distance between outer edges of the first and second first dummy structures ranges between about 100% and about 250% of a distance between outer edges of the first and second metal lines;
a distance between outer edges of the first and second second dummy structures ranges between about 100% and about 250% of a distance between outer edges of the first and second metal lines;
a distance between outer edges of the first and second first dummy structures ranges between about 100% and about 250% of a distance between outer edges of the first and second metal lines; and
a distance between outer edges of the first and second second dummy structures ranges between about 100% and about 250% of a distance between outer edges of the first and second metal lines.

15. An apparatus, comprising:
a substrate;
a first dielectric layer disposed over the substrate;
a second dielectric layer disposed over the substrate;
a plurality of through-silicon-vias (TSVs) extending through the first dielectric layer and the second dielectric layer and into the substrate;
a plurality of metal pads disposed in the second dielectric layer, wherein each of the TSVs is located below a corresponding one of the metal pads;
a plurality of metal lines disposed in the second dielectric layer, the metal lines having a first width;
a plurality of first dummy structures disposed in the second dielectric layer, the first dummy structures having a second width at least three times greater than the first width of the metal lines; and
a plurality of second dummy structures disposed in the second dielectric layer, the second dummy structures having a third width at least five times greater than the second width of the metal lines.

16. The apparatus of claim 15 wherein the first dielectric layer comprises an etch-stop layer and an isolation layer.

17. The apparatus of claim 15 wherein a central axis of each of the TSVs is substantially coincident with a central axis of the corresponding one of the metal pads.

18. The apparatus of claim 15 , further comprising a liner layer along a bottom surface and sidewalls of the TSVs.

19. The apparatus of claim 15 , wherein a top surface of the metal pads, a top surface of the metal lines, a top surface of the first dummy structures, and a top surface of the second dummy structures are substantially co-planar with a top surface of the second dielectric layer.

20. The apparatus of claim 15 , further comprising a second plurality of metal pads, the second plurality of metal pads having a substantially similar composition as the plurality of metal pads.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Pei-Ching
• Chen Yi-Hsiu
• Yeh Jun-Lin
• Lin Yung-Chi
• Hsu Li-Han
• Wu Wei-Cheng
• Yang Ku-Feng
• Chiou Wen-Chih

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title