Multi-stack package-on-package structures

Patent metadata

Field	Value
Publication number	US-9735131-B2
Application number	US-201514972622-A
Country	US
Kind code	B2
Filing date	Dec 17, 2015
Priority date	Nov 10, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein.

First claim

What is claimed is:

1. A method comprising:
placing a first device die over a carrier;
encapsulating the first device die in a first encapsulating material;
performing a first planarization to reveal first metal pillars in the first device die;
forming first dielectric layers over the first device die and the first encapsulating material;
forming first redistribution lines in the first dielectric layers, wherein the first redistribution lines are electrically coupled to the first metal pillars;
adhering a second device die to a top surface of the first dielectric layers;
forming a first through-via over the first dielectric layers;
encapsulating the second device die and substantially an entirety of the first through-via in a second encapsulating material;
performing a second planarization to reveal the first through-via and second metal pillars in the second device die;
forming second dielectric layers over the second device die; and
forming second redistribution lines in the second dielectric layers, wherein the second redistribution lines are electrically coupled to the second metal pillars and the first through-via.

2. The method of claim 1 further comprising:
forming a second through-via, wherein the first encapsulating material encapsulates the second through-via.

3. The method of claim 1 , wherein no through-via penetrates through the first encapsulating material, and the method further comprises:
de-bonding the carrier from the first device die;
performing a backside grinding to expose a second through-via in a semiconductor substrate of the first device die; and
forming additional redistribution lines electrically coupling to the second through-via.

4. The method of claim 3 , wherein the second through-via is electrically decoupled from all active devices in the first device die.

5. The method of claim 4 , wherein the second through-via is electrically decoupled from all passive devices in the first device die.

6. The method of claim 1 further comprising electrically coupling a third device die to the second redistribution lines, wherein the third device die is encapsulated in a third encapsulating material.

7. The method of claim 6 further comprising:
adhering the third device die to a top surface of the second dielectric layers;
forming addition through-vias over the second dielectric layers, wherein the additional through-vias are electrically coupled to second first redistribution lines;
encapsulating the third device die in a third encapsulating material;
performing a third planarization to reveal third metal pillars in the third device die; and
forming third redistribution lines electrically coupling to the third metal pillars.

8. A method comprising:
placing a first device die over a carrier, wherein the first device die comprises:
a first semiconductor substrate; and
first through-vias penetrating through the first semiconductor substrate;

encapsulating the first device die in a first encapsulating material;
forming first dielectric layers over the first device die;
forming first redistribution lines in the first dielectric layers, wherein the first redistribution lines are electrically coupled to first metal pillars in the first device die;
adhering a second device die to a top surface of the first dielectric layers;
forming second through-vias over the first dielectric layers, wherein the second through-vias are electrically coupled to the first redistribution lines;
encapsulating the second device die in a second encapsulating material;
forming second dielectric layers over the second device die;
forming second redistribution lines in the second dielectric layers, wherein the second redistribution lines are electrically coupled to second metal pillars in the second device die;
de-bonding the carrier from the first device die;
performing a backside grinding on the first semiconductor substrate to reveal the first through-vias; and
forming third redistribution lines to electrically couple to the first through-vias.

9. The method of claim 8 , wherein the first through-vias are electrically decoupled from all active devices in the first device die.

10. The method of claim 9 , wherein the first through-vias are further electrically decoupled from all passive devices in the first device die.

11. The method of claim 8 further comprising:
performing a planarization to make a top surface of the first encapsulating material and top surfaces of first metal pillars to be coplanar, wherein the first dielectric layers are planar layers.

12. A method comprising:
adhering a back surface of a first device die to a base polymer layer through a first adhesive;
forming first metal posts over the base polymer layer;
encapsulating the first device die and the first metal posts in a first encapsulating material;
forming first polymer layers over the first device die and the first encapsulating material;
forming first redistribution lines in the first polymer layers, wherein the first redistribution lines are electrically coupled to the first device die;
adhering a back surface of a second device die to a top surface of the first polymer layers through a second adhesive;
forming second metal posts over the first polymer layers;
encapsulating the second device die and substantially an entirety of the second metal posts in a second encapsulating material;
forming second polymer layers over the second device die and the second encapsulating material; and
forming second redistribution lines in the second polymer layers, wherein the second redistribution lines are electrically coupled to the second device die.

13. The method of claim 12 , wherein the first device die comprises a semiconductor substrate and through-vias in the semiconductor substrate, and the method further comprises:
performing a backside grinding on the first adhesive and the semiconductor substrate to reveal the through-vias; and
forming third redistribution lines to electrically couple to the through-vias.

14. The method of claim 13 , wherein in the backside grinding, the first metal posts are ground.

15. The method of claim 13 , wherein in the backside grinding, the base polymer layer is ground.

16. The method of claim 12 further comprising:
forming openings in the base polymer layer; and
forming solder regions extending into the openings.

17. The method of claim 16 , wherein the solder regions are in physical contact with the first metal posts.

18. The method of claim 12 , wherein the back surface of the first device die and the back surface of the second device die are both surfaces of semiconductor materials.

19. The method of claim 12 , wherein in the forming the second metal posts, a metallic material is filled into openings in the second polymer layers.

20. The method of claim 12 , wherein the first polymer layers and the second polymer layers are formed of polybenzoxazole (PBO).

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Su An-Jhih
• Yu Chen-Hua

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title