3DIC stacking device and method of manufacture

Patent metadata

Field	Value
Publication number	US-9443783-B2
Application number	US-201213619877-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Jun 27, 2012
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

First claim

What is claimed is:

1. A method for forming a device comprising:
placing two or more bottom dies on a first carrier wafer;
forming a first molding compound between the two or more bottom dies such that electrical contacts on the two or more bottom dies are exposed, wherein the exposed electrical contacts are located on a side of the two or more bottom dies that faces away from the first carrier wafer, wherein the exposed electrical contacts on the two or more bottom dies are exposed using at least in part a grinding process;
attaching the two or more bottom dies and the first molding compound to a second carrier wafer with an adhesive, wherein the adhesive is in physical contact with the electrical contacts;
thinning the two or more bottom dies to expose through vias formed through the two or more bottom dies, wherein the thinning the two or more bottom dies is performed on an opposite side of the two or more bottom dies than the exposed electrical contacts side;
forming electrical contacts to the through vias along a backside of the two or more bottom dies; and
attaching one or more top dies to the one or more bottom dies.

2. The method of claim 1 , wherein the first molding compound covers a bottom side of the two or more bottom dies.

3. The method of claim 1 , wherein the forming a first molding compound comprises thinning the first molding compound to expose the electrical contacts on the two or more bottom dies.

4. The method of claim 1 , further comprising forming a redistribution layer formed over the two or more bottom dies.

5. The method of claim 4 , wherein the redistribution layer extends over the first molding compound.

6. The method of claim 1 , further comprising a second molding compound formed over the one or more top dies.

7. A method of manufacturing a semiconductor device, the method comprising:
attaching a first semiconductor die to a carrier, the first semiconductor die comprising first external contacts, wherein a surface of the first external contacts facing away from the carrier is covered by a polymer material;
attaching a second semiconductor die to the carrier, the second semiconductor die comprising second external contacts;
encapsulating the first semiconductor die and the second semiconductor die with an encapsulant different from the polymer material, wherein the encapsulant is a single material;
removing a portion of the encapsulant to expose a first surface of the first external contacts and a second surface of the second external contacts, wherein the first surface and the second surface face away from the carrier;
attaching the first external contacts to a second carrier with an adhesive, the adhesive being in physical contact with the first external contacts;
thinning the first semiconductor die and the second semiconductor die to remove first semiconductor material from over a first conductive material to expose first through substrate vias in the first semiconductor die and to remove second semiconductor material from over a second conductive material to expose second through substrate vias in the second semiconductor die, wherein the first semiconductor material is on an opposite side of the first semiconductor die than the first surface; and
electrically connecting a third semiconductor die to the first through substrate vias and electrically connecting a fourth semiconductor die to the second through substrate vias, wherein the third semiconductor die has a first width of between about 1 mm and about 20 mm, the first semiconductor die has a second width of between about 3 mm and about 14 mm, and wherein the second width is less than the first width.

8. The method of claim 7 , further comprising encapsulating the third semiconductor die and the fourth semiconductor die.

9. The method of claim 7 , further comprising forming a third external contact on the first external contacts after the encapsulating the first semiconductor die and the second semiconductor die.

10. The method of claim 7 , further comprising forming a redistribution layer in electrical connection with the first external contacts.

11. The method of claim 10 , wherein the forming the redistribution layer occurs prior to the thinning the first semiconductor die and the second semiconductor die.

12. The method of claim 10 , further comprising forming third external contacts in electrical connection with the redistribution layer after the electrically connecting the third semiconductor die to the first through substrate vias.

13. The method of claim 7 , wherein the electrically connecting the third semiconductor die to the first through substrate vias further comprises offsetting the third semiconductor die from the first semiconductor die.

14. The method of claim 7 , wherein the third semiconductor die overhangs the first semiconductor die after the electrically connecting the third semiconductor die to the first through substrate vias.

15. A method of manufacturing a semiconductor device, the method comprising:
attaching a first semiconductor die to a carrier wafer, the first semiconductor die comprising first electrical contacts facing away from the carrier wafer and a first surface facing towards the carrier wafer;
attaching a second semiconductor die to the carrier wafer, the second semiconductor die comprising second electrical contacts facing away from the carrier wafer and a second surface facing towards the carrier wafer;
encapsulating the first semiconductor die and the second semiconductor die with molding compound, wherein a first portion of the molding compound is over and in direct physical contact with the first semiconductor die and a second portion of the molding compound is over and in direct physical contact with the second semiconductor die;
grinding the first portion of the molding compound and the second portion of the molding compound over the first semiconductor die and the second semiconductor die until the first electrical contacts and the second electrical contacts have been exposed by the grinding;
applying an adhesive to be in physical contact with the first electrical contacts and the second electrical contacts and adhering the first electrical contacts and the second electrical contacts to a second carrier wafer with the adhesive;
subsequent to the grinding the first portion of the molding compound and the second portion of the molding compound, removing a portion of the first surface over first vias and removing a portion of the second surface over second vias to thin the first semiconductor die and the second semiconductor die and expose first through vias and second through vias, wherein the first vias were covered by the first surface prior to the removing the portion of the first surface;
forming a first redistribution layer in electrical connection with the first through vias;
attaching a third semiconductor die to the first redistribution layer;
attaching a fourth semiconductor die to the first redistribution layer;
encapsulating the third semiconductor die and the fourth semiconductor die with an encapsulant, wherein the first redistribution layer is located between the encapsulant and the molding compound in a direction perpendicular with a major surface of the first semiconductor device; and
grinding the encapsulant to expose the third semiconductor die and the fourth semiconductor die.

16. The method of claim 15 , further comprising forming a second redistribution layer in electrical connection with the first electrical contacts.

17. The method of claim 16 , wherein the forming the second redistribution layer occur

Assignees

• Lin Jing-Cheng
• Yu Chen-Hua
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Yu Chen-Hua

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title