Plural gate oxide structures with different thicknesses in semiconductor devices

Patent metadata

Field	Value
Publication number	US-12369385-B2
Application number	US-202418600216-A
Country	US
Kind code	B2
Filing date	Mar 8, 2024
Priority date	Sep 25, 2020
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first gate structure, disposed on the substrate, comprising:
a first oxide layer of a first thickness disposed on a first channel region,
a second oxide layer of a second thickness disposed on the first oxide layer, and
a first metal layer disposed on the second oxide layer; and

a second gate structure, disposed on the substrate, comprising:
a third oxide layer of a third thickness disposed on a second channel region,
a fourth oxide layer of a fourth thickness disposed on the third oxide layer, and
a second metal layer disposed on the fourth oxide layer,

wherein:
the first and third thicknesses are different from each other,
the second and fourth thicknesses are substantially equal to each other, and
a material of the second oxide layer is different from a material of the fourth oxide layer.

2. The semiconductor device of claim 1 , further comprising a high-k dielectric layer disposed between the first oxide layer and the second oxide layer.

3. The semiconductor device of claim 1 , further comprising a high-k dielectric layer disposed between the third oxide layer and the fourth oxide layer.

4. The semiconductor device of claim 1 , further comprising a first dielectric layer disposed between the first oxide layer and the second oxide layer, wherein the first dielectric layer comprises rare-earth metal dopants.

5. The semiconductor device of claim 4 , further comprising a second dielectric layer disposed directly on the first dielectric layer, wherein the second dielectric layer comprises a dielectric constant greater than a dielectric constant of the first dielectric layer.

6. The semiconductor device of claim 1 , further comprising a layer of dipoles disposed between the first oxide layer and the second oxide layer.

7. The semiconductor device of claim 1 , wherein a material of the first oxide layer is the same as a material of the third oxide layer.

8. The semiconductor device of claim 1 , wherein a thickness of the first channel region is greater than a thickness of the second channel region.

9. The semiconductor device of claim 1 , wherein the second and fourth oxide layers have oxygen diffusivities different from each other.

10. The semiconductor device of claim 1 , wherein the second and fourth oxide layers have Gibbs energies different from each other.

11. A semiconductor device, comprising:
a substrate;
a first transistor, disposed on the substrate, comprising:
a first nanostructured channel region,
a first oxide layer surrounding the first nanostructured channel region, and
a second oxide layer disposed on the first oxide layer, and

a second transistor, disposed on the substrate, comprising:
a second nanostructured channel region,
a third oxide layer surrounding the second nanostructured channel region, and
a fourth oxide layer disposed on the third oxide layer,

wherein:
a thickness of the first oxide layer is different from a thickness of the third oxide layer, and
a thickness of the first nanostructured channel region is different from a thickness of the second nanostructured channel region.

12. The semiconductor device of claim 11 , wherein the second oxide layer and the fourth oxide layer comprise oxynitride layers.

13. The semiconductor device of claim 11 , further comprising:
a first dielectric layer comprising hafnium oxide disposed directly on the first oxide layer; and
a second dielectric layer comprising zirconium oxide disposed directly on the first dielectric layer.

14. The semiconductor device of claim 11 , wherein the second and fourth oxide layers have oxygen diffusivities different from each other.

15. The semiconductor device of claim 11 , wherein the second and fourth oxide layers have Gibbs energies different from each other.

16. The semiconductor device of claim 11 , wherein a material of the first oxide layer is the same as a material of the third oxide layer.

17. A semiconductor device, comprising:
a substrate;
a first nanostructured channel region disposed on the substrate;
a second nanostructured channel region disposed on the first nanostructured channel region; and
a gate structure surrounding the first and second nanostructured channel regions, wherein the gate structure comprises:
first and second oxide layers surrounding the first and second nanostructured channel regions, respectively;
first and second high-k dielectric layers disposed on the first and second oxide layers, respectively; and
third and fourth oxide layers disposed on the first and second high-k dielectric layers, respectively,
wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer, and
wherein a thickness of the second nanostructured channel region is greater than a thickness of the first nanostructured channel region.

18. The semiconductor device of claim 17 , wherein the first oxide layer comprises an oxide of a material of the first nanostructured channel region.

19. The semiconductor device of claim 17 , wherein the first high-k dielectric layer comprises:
a hafnium oxide layer disposed directly on the first oxide layer; and
a zirconium oxide layer disposed directly on the hafnium oxide layer.

20. The semiconductor device of claim 17 , wherein the first high-k dielectric layer comprises rare earth metal dopants.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chung-Liang

Classifications

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title