Infrared debond damage mitigation by copper fill pattern

Patent metadata

Field	Value
Publication number	US-12300615-B2
Application number	US-202218056393-A
Country	US
Kind code	B2
Filing date	Nov 17, 2022
Priority date	Nov 17, 2022
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

First claim

What is claimed is:

1. A stack structure comprising:
a device wafer;
a handler wafer; and
a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy,
wherein the device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

2. The stack structure of claim 1 , wherein the at least two consecutive layers are at least a portion of a back-end-of-line (BEOL) structure.

3. The stack structure of claim 1 , wherein the plurality of layers of the device wafer below the two consecutive layers include a front-end-of-line (FEOL) structure.

4. The stack structure of claim 1 , wherein the plurality of fill portions provide coverage across the device wafer from a first side to a second side to form a fill overlap layer.

5. The stack structure of claim 4 , wherein the fill overlap layer is configured to substantially or completely mitigate damage to a plurality of devices included in the plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

6. The stack structure of claim 1 , wherein the bonding structure removably binds the device wafer and the handler wafer together.

7. The stack structure of claim 1 , wherein the infrared laser energy causes debonding and release of the device wafer from the handler wafer as a direct result of a substantial or a complete vaporization of at least a portion of the bonding structure.

8. A method for handling a device wafer, the method comprising:
bonding a handler wafer to a device wafer using a bonding structure that includes an adhesive layer and a release layer, wherein the device wafer includes a plurality of layers and at least two consecutive layers of the plurality of layers include a plurality of fill portions that substantially or completely disable entry of an infrared laser energy into a plurality of layers of the device wafer below the at least two consecutive layers that include the plurality of fill portions;
processing the device wafer while bonded to the handler wafer; and
debonding the device wafer and the handler wafer by irradiating the release layer with the infrared laser energy through the handler wafer.

9. The method of claim 8 , wherein the at least two consecutive layers that include the plurality of fill portions are at least a portion of a back-end-of-line (BEOL) structure.

10. The method of claim 8 , wherein the plurality of fill portions provide coverage across the device wafer from a first side to a second side to form a fill overlap layer.

11. The method of claim 10 , wherein the fill overlap layer is configured to substantially or completely mitigate damage to a plurality of devices included in the plurality of layers of the device wafer below the two consecutive layers.

12. The method of claim 10 , wherein the fill overlap layer includes a fill material of copper.

13. The method of claim 8 , wherein the infrared laser energy substantially or completely vaporizes the release layer such that the device wafer is released from the handler wafer as a direct result of a substantial or a complete vaporization of the release layer.

14. The method of claim 8 , wherein the plurality of layers of the device wafer below the two consecutive layers that include the plurality of fill portions include a front-end-of-line (FEOL) structure.

15. A method of making a semiconductor stack structure, the method comprising:
forming a device wafer by
forming a device layer including a plurality of devices, and
forming at least two consecutive layers on a surface of the device layer that include a plurality of fill portions;

forming a handler wafer;
removably bonding the handler wafer to the device wafer using a bonding structure including an adhesive layer and a release layer, wherein the adhesive layer is applied to one of the at least two consecutive layers that include the plurality of fill portions; and
exposing an infrared laser energy to the semiconductor stack structure through the handler wafer to cause debonding and release of the device wafer from the handler wafer as a direct result of a substantial or a complete vaporization of at least a portion of the bonding structure,
wherein the plurality of fill portions are configured to substantially or completely disable entry of the infrared laser energy into the device wafer below the two consecutive layers that include the plurality of fill portions.

16. The method of claim 15 , wherein the at least two consecutive layers that include the plurality of fill portions are at least a portion of a back-end-of-line (BEOL) structure.

17. The method of claim 15 , wherein the plurality of layers of the device wafer below the two consecutive layers, that include the plurality of fill portions, include a front-end-of-line (FEOL) structure.

18. The method of claim 15 , wherein the plurality of fill portions provide coverage across the device wafer from a first side to a second side to form a fill overlap layer.

19. The method of claim 18 , wherein the fill overlap layer includes a fill material of copper.

20. The method of claim 18 , wherein the fill overlap layer is configured to substantially or completely mitigate damage to the plurality of devices included in the plurality of layers of the device wafer below the at least two consecutive layers that include the plurality of fill portions.

Assignees

• IBM

Inventors

• Farooq Mukta Ghate
• Chen Qianwen
• Butt Shahid
• Perfecto Eric
• Belyansky Michael P
• Sakuma Katsuyuki
• Knickerbocker John

Classifications

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10P72/7428

  used to support diced chips prior to mounting · CPC title

• H10P72/7426

  used as a support during build up manufacturing of active devices · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/7412

  the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title