Polyimides as laser release materials for 3-D IC applications

US9827740B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9827740-B2
Application numberUS-201514805898-A
CountryUS
Kind codeB2
Filing dateJul 22, 2015
Priority dateJul 22, 2014
Publication dateNov 28, 2017
Grant dateNov 28, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The invention broadly relates to release layer compositions that enable thin wafer handling during microelectronics manufacturing. Preferred release layers are formed from compositions comprising a polyamic acid or polyimide dissolved or dispersed in a solvent system, followed by curing and/or solvent removal at about 250° C. to about 350° C. for less than about 10 minutes, yielding a thin film. This process forms the release compositions into polyimide release layers that can be used in temporary bonding processes, and laser debonded after the desired processing has been carried out.

First claim

Opening claim text (preview).

We claim: 1. A temporary bonding method comprising: providing a stack comprising: a first substrate having a back surface and a front surface; a bonding layer adjacent said front surface; and a second substrate having a first surface, said first surface including a polyimide release layer adjacent said bonding layer, wherein said polyimide release layer is formed from a composition comprising a polymer dissolved or dispersed in a solvent system, said polymer comprising recurring monomers selected from the group consisting of fluorinated dianhydrides, photosensitive dianhydrides, photosensitive diamines, and combinations thereof; and exposing said polyimide release layer to laser energy so as to facilitate separation of said first and second substrates. 2. The method of claim 1 , said release layer having an average thickness of less than about 50 μm. 3. The method of claim 1 , wherein said exposing is carried out at a dosage of from about 100 mJ/cm 2 to about 400 mJ/cm 2 . 4. The method of claim 1 , wherein said polymer comprises recurring monomers selected from the group consisting of 2,2′-bis-(dicarboxyphenyl)hexafluoropropane dianhydride, 3,3′,4,4′-benzophenone tetracarboxylic dianhydride, 9,9′-bis(4-aminophenyl) fluorine, 5(6)-amino-1-(4′ aminophenyl)-1,3,-trimethylindane, and combinations thereof. 5. The method of claim 1 , said solvent system comprising a solvent selected from the group consisting of cyclohexanone, cyclopentanone, propylene glycol monomethyl ether, gamma-butyrolactone, ethyl 3-ethoxypropionate, propoxy propanol, propylene glycol methyl ether acetate, ethyl lactate, and mixtures thereof. 6. The method of claim 1 , further comprising forming said release layer by applying said composition to said first surface. 7. The method of claim 6 , further comprising heating said composition at a temperature of from about 250° C. to about 350° C. for a time period of less than about 10 minutes. 8. The method of claim 1 , wherein said bonding layer is formed from a composition comprising a polymer or oligomer dissolved or dispersed in a solvent system, said polymer or oligomer being selected from the group consisting of polymers and oligomers of cyclic olefins, epoxies, acrylics, styrenics, vinyl halides, vinyl esters, polyamides, polyimides, polysulfones, polyethersulfones, cyclic olefins, polyolefin rubbers, polyurethanes, ethylene-propylene rubbers, polyamide esters, polyimide esters, polyacetals, and polyvinyl buterol. 9. The method of claim 1 , wherein said front surface is a device surface that comprises an array of devices selected from the group consisting of integrated circuits; MEMS; microsensors; power semiconductors; light-emitting diodes; photonic circuits; interposers; embedded passive devices; and microdevices fabricated on or from silicon, silicon-germanium, gallium arsenide, and gallium nitride. 10. The method of claim 1 , wherein said first surface is a device surface that comprises an array of devices selected from the group consisting of integrated circuits; MEMS; microsensors; power semiconductors; light-emitting diodes; photonic circuits; interposers; embedded passive devices; and microdevices fabricated on or from silicon, silicon-germanium, gallium arsenide, and gallium nitride. 11. The method of claim 1 , wherein said second substrate comprises glass or other transparent material. 12. The method of claim 1 , wherein said first substrate comprises glass or other transparent material. 13. The method of claim 1 , wherein said front surface is a device surface comprising at least one structure selected from the group consisting of: solder bumps; metal posts; metal pillars; and structures formed from a material selected from the group consisting of silicon, polysilicon, silicon dioxide, silicon (oxy)nitride, metal, low k dielectrics, polymer dielectrics, metal nitrides, and metal silicides. 14. The method of claim 1 , wherein said first surface is a device surface comprising at least one structure selected from the group consisting of: solder bumps; metal posts; metal pillars; and structures formed from a material selected from the group consisting of silicon, polysilicon, silicon dioxide, silicon (oxy)nitride, metal, low k dielectrics, polymer dielectrics, metal nitrides, and metal silicides. 15. The method of claim 1 , further comprising subjecting said stack to processing selected from the group consisting of back-grinding, chemical-mechanical polishing, etching, metallizing, dielectric deposition, patterning, passivation, annealing, and combinations thereof, prior to separating said first and second substrates, prior to separating said first and second substrates.

Assignees

Inventors

Classifications

  • used to protect an active side of a device or wafer · CPC title

  • used during dicing or grinding · CPC title

  • the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title

  • Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

  • using temporarily an auxiliary support · CPC title

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What does patent US9827740B2 cover?
The invention broadly relates to release layer compositions that enable thin wafer handling during microelectronics manufacturing. Preferred release layers are formed from compositions comprising a polyamic acid or polyimide dissolved or dispersed in a solvent system, followed by curing and/or solvent removal at about 250° C. to about 350° C. for less than about 10 minutes, yielding a thin film…
Who is the assignee on this patent?
Brewer Science Inc
What technology area does this patent fall under?
Primary CPC classification B32B7/06. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Nov 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).