Method of forming an integrated circuit devices having buried word lines

Patent metadata

Field	Value
Publication number	US-12207456-B2
Application number	US-202318525187-A
Country	US
Kind code	B2
Filing date	Nov 30, 2023
Priority date	Apr 21, 2021
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a substrate comprising an active region;
a word line disposed inside a word line trench formed in the substrate and extending in a first direction parallel to a top surface of the substrate;
a bit line extending on the substrate in a second direction perpendicular to the first direction;
a gate insulation layer disposed on inner walls of the word line trench and surrounding sidewalls and a bottom surface of the word line; and
a gate capping layer disposed inside the word line trench and on the word line,
wherein the word line trench comprises:
a lower portion having a first width in the second direction;
an upper portion disposed at a level higher than that of the lower portion and having a second width greater than the first width of the lower portion in the second direction; and
an inflection portion defined between the lower portion and the upper portion.

2. The integrated circuit device of claim 1 , wherein sidewalls of the upper portion extend outward with respect to the lower portion.

3. The integrated circuit device of claim 1 , wherein the second width is from about 110% to about 200% of the first width.

4. The integrated circuit device of claim 1 , wherein a width of the word line trench varies discontinuously at the inflection portion, and
an inclination of sidewalls of the word line trench varies rapidly at the inflection portion.

5. The integrated circuit device of claim 1 , further comprising an insulation liner disposed on inner walls of the upper portion of the word line trench and covering sidewalls of the gate insulation layer.

6. The integrated circuit device of claim 5 , wherein a bottom portion of the insulation liner surrounds the inflection portion.

7. The integrated circuit device of claim 5 , wherein a bottom surface of the insulation liner is at a level higher than that of a top surface of the word line.

8. The integrated circuit device of claim 5 , wherein a bottom surface of the insulation liner is at a level lower than that of a top surface of the word line.

9. The integrated circuit device of claim 1 , wherein the gate capping layer comprises:
a first portion disposed inside the upper portion of the word line trench; and
a second portion disposed inside the lower portion of the word line trench, and
a third width of the first portion in the second direction is greater than a fourth width of the second portion in the second direction.

10. The integrated circuit device of claim 1 , wherein a top surface of the word line is at a level higher than that of the inflection portion, and
the word line comprises an extended portion protruding in lateral directions at a level higher than that of the inflection portion.

11. An integrated circuit device, comprising:
a substrate comprising an active region;
a word line disposed inside a word line trench formed in the substrate and extending in a first direction parallel to a top surface of the substrate;
a bit line extending on the substrate in a second direction perpendicular to the first direction;
a gate insulation layer disposed on inner walls of the word line trench and surrounding sidewalls and a bottom surface of the word line;
a gate capping layer disposed inside the word line trench and on the word line and comprising an upper portion having a width greater than a width of the word line in the second direction; and
an insulation liner disposed on sidewalls of the upper portion of the word line trench and between the gate insulation layer and the substrate.

12. The integrated circuit device of claim 11 , wherein the word line trench comprises:
a lower portion having a first width in the second direction;
an upper portion disposed above the lower portion and having a second width greater than the first width in the second direction; and
an inflection portion defined between the lower portion and the upper portion.

13. The integrated circuit device of claim 12 , wherein a width of the word line trench varies discontinuously at the inflection portion, and
wherein sidewalls of the upper portion extend outward with respect to the lower portion.

14. The integrated circuit device of claim 12 , wherein a bottom portion of the insulation liner surrounds the inflection portion.

15. The integrated circuit device of claim 12 , wherein the insulation liner extends to the inflection portion along inner walls of the upper portion of the word line trench, and
a bottom surface of the gate capping layer is at a vertical level lower than that of the inflection portion.

16. The integrated circuit device of claim 15 , wherein the gate capping layer comprises:
a first portion disposed inside the upper portion of the word line trench; and
a second portion disposed inside the lower portion of the word line trench, and
a third width of the first portion in the second direction is greater than a fourth width of the second portion in the second direction.

17. The integrated circuit device of claim 12 , wherein a bottom surface of the gate capping layer is at a vertical level higher than that of the inflection portion, and
the word line comprises an extended portion protruding in lateral directions at a level higher than that of the inflection portion.

18. An integrated circuit device, comprising:
a substrate comprising an active region;
a word line trench formed in the substrate, extending in a first direction parallel to a top surface of the substrate, and comprising a lower portion having a first width in a second direction perpendicular to the first direction and an upper portion having a second width greater than the first width in the second direction;
a word line disposed inside the word line trench and extending in the first direction;
a gate insulation layer disposed on inner walls of the word line trench and surrounding sidewalls and a bottom surface of the word line;
a gate capping layer disposed on inner walls of the word line trench and on the word line;
an insulation liner disposed on the upper portion of the word line trench and between the gate insulation layer and the substrate;
a bit line extending in the second direction on the substrate; and
a direct contact disposed between the active region of the substrate and the bit line.

19. The integrated circuit device of claim 18 , wherein the gate capping layer comprises:
a first portion disposed inside the upper portion of the word line trench; and
a second portion disposed inside the lower portion of the word line trench, and
a third width of the first portion in the second direction is greater than a fourth width of the second portion in the second direction.

20. The integrated circuit device of claim 18 , wherein the word line trench further comprises an inflection portion defined between the upper portion and the lower portion,
the insulation liner extends to the inflection portion along inner walls of the upper portion of the word line trench, and
a bottom surface of the gate capping layer is at a vertical level lower than that of the inflection portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Taejin
• Kim Taehoon
• Kim Kyujin
• Park Chulkwon
• Han Sunghee
• Hwang Yoosang

Classifications

• H10W15/01

  Manufacture or treatment · CPC title

• H10W15/00 Primary

  Highly-doped buried regions of integrated devices · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10B12/482

  Bit lines · CPC title