Methods of fabricating semiconductor devices having buried channel array

Patent metadata

Field	Value
Publication number	US-9276074-B2
Application number	US-201313761376-A
Country	US
Kind code	B2
Filing date	Feb 7, 2013
Priority date	Apr 30, 2012
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a first field region extending in a first direction in a substrate;
forming a pair of buried gate structures extending across the first field region at a predetermined angle with respect to the first direction; and
forming a second field region extending in substantially parallel with the buried gate structure, wherein the first field region intersects with the second field region at an intersection region, the intersection region having greater depth than that of the first and the second field regions,
wherein the forming the pair of buried gate structure comprises:
forming a gate mask pattern having a pair of gate trench holes on the substrate;
forming a pair of gate trenches in the substrate using the gate mask pattern as an etch mask; and
forming a pair of gate capping layers to fill the pair of gate trenches, and

wherein the forming the second field region comprises:
recessing the gate mask pattern partially so that each of the gate capping layers includes an upper portion exposed from the recessed the gate mask pattern;
forming a spacer mask pattern on side surfaces of the upper portions of the gate capping layers and on the recessed gate mask pattern;
etching the substrate using the spacer mask pattern as an etch mask to form a second field trench in the substrate; and
forming a second field insulating material to fill the second field trench.

2. The method of claim 1 , wherein the forming the spacer mask pattern comprises:
forming a spacer mask material layer to cover the gate capping layers and the recessed gate mask pattern;
etching the spacer mask material layer to expose a portion of the gate mask pattern; and
etching the exposed portion of the gate mask pattern to form a field trench hole exposing the surface of the substrate.

3. The method of claim 2 , wherein the forming the gate mask pattern comprises:
forming a pad insulating layer on the substrate;
forming a buffer insulating layer on the pad insulating layer; and
forming the gate mask pattern on the buffer insulating layer.

4. The method of claim 3 , further comprising:
removing the spacer mask pattern to expose the gate mask pattern after forming the second field insulating material.

5. The method of claim 4 , further comprising:
removing the exposed gate mask pattern so that the buffer insulating layer is exposed,
the upper portions of the pair of gate capping layers are exposed, and an upper portion of the second field insulating material is exposed.

6. The method of claim 5 , further comprising:
forming a sacrificial layer on the exposed buffer insulating layer, the exposed upper portions of the pair of gate capping layers and the exposed upper portion of the second field insulating material.

7. The method of claim 6 , further comprising:
removing the sacrificial layer over the first field region to form a landing pad trench.

8. The method of claim 7 , further comprising:
forming a landing pad insulating layer including silicon nitride to fill the landing pad trench.

9. The method of claim 8 , further comprising:
removing the landing pad insulating layer partially so that top surfaces of the landing pad insulating layer, the gate capping layer and the second field insulating material are substantially planarized.

10. The method of claim 9 , further comprising:
removing a remaining portion of the sacrificial layer to form a landing pad hole defined by the landing pad insulating layer and the pair of gate capping layers.

11. The method of claim 10 , further comprising:
removing the landing pad insulating layer and the gate capping layers partially so that the landing pad hole is expanded and overlap the buried gate structures partially.

12. The method of claim 11 , further comprising:
forming a landing pad in the landing pad hole, the landing pad overlapping the buried gate structures partially.

Assignees

• Choi Jay-Bok
• Hwang Yoo-Sang
• Kim Ah-Young
• Lee Ye-Ro
• Jin Gyo-Young
• Hong Hyeong-Sun
• Samsung Electronics Co Ltd

Inventors

• Choi Jay-Bok
• Hwang Yoo-Sang
• Kim Ah-Young
• Lee Ye-Ro
• Jin Gyo-Young
• Hong Hyeong-Sun

Classifications

• H10D64/027

  by etching at gate locations · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/311 Primary

  Gate electrodes for field-effect devices · CPC title

• H01L29/66621

  Electricity · mapped topic