Method of forming semiconductor memory device comprises a bit line having a plurality of pins extending along a direction being perpendicular to a substrate

Patent metadata

Field	Value
Publication number	US-11600622-B2
Application number	US-202117336319-A
Country	US
Kind code	B2
Filing date	Jun 2, 2021
Priority date	May 8, 2021
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

The present disclosure relates to a fabricating method of a semiconductor memory device including the following steps. Firstly, a substrate is provided, and a plurality of gate structures is formed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. Next, a plurality of isolation fins is formed on the substrate, wherein each of the isolation fins is parallel with each other and extends along the first direction, over each of the gate structures respectively. After forming the isolation fins, at least one bit line is formed on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending along a direction being perpendicular to the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

First claim

What is claimed is:

1. A method of fabricating a semiconductor memory device, comprising:
providing a substrate;
forming a plurality of gate structures in the substrate, each of the gate structures being parallel with each other and extending along a first direction;
forming a plurality of isolation fins on the substrate, each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively; and
after forming the isolation fins, forming at least one bit line on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending along a direction being perpendicular to the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

2. The method of fabricating the semiconductor memory device according to claim 1 , wherein the forming of the isolation fins comprising:
forming a plurality of primary isolation fins on the substrate; and
patterning the primary isolation fins to form the isolation fins.

3. The method of fabricating the semiconductor memory device according to claim 2 , wherein the forming of the isolation fins comprising:
forming an isolation layer on the substrate;
forming a plurality of trenches in the isolation layer, each of the trenches being parallel with each other and extending along the first direction, over each of the gate structures; and
forming the primary isolation fins in the trenches.

4. The method of fabricating the semiconductor memory device according to claim 3 , wherein the at least one bit line comprises a plurality of first pins and a plurality of second pins, the first pins not directly contact the substrate, and the second pins directly contact the substrate.

5. The method of fabricating the semiconductor memory device according to claim 4 , wherein first pins and the second pins are alternately arranged with the isolation fins along the second direction.

6. The method of fabricating the semiconductor memory device according to claim 4 , wherein each of the second pins is formed between any two of the first pins.

7. The method of fabricating the semiconductor memory device according to claim 4 , wherein the forming of the at least bit line comprising:
forming a first photoresist structure on the isolation layer to form a trench opening;
forming a second photoresist structure on the isolation layer to form a via opening; and
forming the first pin in the trench opening and forming the second pin in the via opening.

8. The method of fabricating the semiconductor memory device according to claim 7 , wherein the trench opening is formed before the via opening.

9. The method of fabricating the semiconductor memory device according to claim 7 , wherein the via opening is formed before the trench opening.

10. The method of fabricating the semiconductor memory device according to claim 7 , wherein the via opening and the trench opening are formed simultaneously.

11. The method of fabricating the semiconductor memory device according to claim 7 , wherein the trench opening and the via opening are formed through a dual damascene process.

12. The method of fabricating the semiconductor memory device according to claim 7 , wherein the first pins and the second pins are connected with each other.

13. The method of fabricating the semiconductor memory device according to claim 7 , further comprising:
after forming the trench opening and the via opening, forming a plurality of isolation structures on the substrate, between the isolation fins and the at least one bit lines, wherein the isolation structure and the isolation fins comprises different materials.

14. The method of fabricating the semiconductor memory device accordingly to claim 13 , wherein a top surface of a portion of the isolation fins is lower than a top surface of the isolation structures.

15. The method of fabricating the semiconductor memory device according to claim 1 , further comprising:
forming a first pacer on sidewalls of the at least one bit line; and
forming a second spacer on sidewalls of the isolation fins, wherein the first spacer and the second spacer structure are simultaneously formed.

16. The method of fabricating the semiconductor memory device according to claim 15 , wherein the first spacer and the second spacer are formed before the forming of the at least one bit line.

17. The method of fabricating the semiconductor memory device accordingly to claim 16 , wherein the isolating layer comprises an oxide-nitride-oxide structure.

18. The method of fabricating the semiconductor memory device according to claim 1 , further comprising:
forming an isolating layer on the substrate, covering the gate structures, and the isolation fins are disposed on the isolating layer.

Assignees

• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Zhang Janbo
• Feng li-wei
• Tung Yu-Cheng

Classifications

• H10B12/485 Primary

  Bit line contacts · CPC title

• H10B12/482 Primary

  Bit lines · CPC title

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title