Integrated circuit device including gate spacer structure

Patent metadata

Field	Value
Publication number	US-10896967-B2
Application number	US-201916404996-A
Country	US
Kind code	B2
Filing date	May 7, 2019
Priority date	Sep 13, 2018
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a gate stack structure on a base layer, the gate stack structure including:
a gate insulating layer, the gate insulating layer including a first dielectric layer on the base layer and having first relative permittivity, and
a gate structure on the gate insulating layer; and

a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer,
wherein the gate insulating layer separates the buried dielectric layer in the recess hole from the gate structure.

2. The integrated circuit device as claimed in claim 1 , wherein:
the base layer includes at least one of a semiconductor substrate and a semiconductor layer, and a memory cell area and a peripheral circuit area on the at least one of the semiconductor substrate and the semiconductor layer, and
the gate insulating layer, the gate structure, and the gate spacer structure are in the peripheral circuit area.

3. The integrated circuit device as claimed in claim 1 , wherein the gate insulating layer further includes a second dielectric layer on the first dielectric layer, the second dielectric layer having second relative permittivity greater than the first relative permittivity.

4. The integrated circuit device as claimed in claim 3 , wherein the first dielectric layer has a greater thickness than the second dielectric layer.

5. The integrated circuit device as claimed in claim 1 , wherein each of the first dielectric layer and the buried dielectric layer includes a silicon oxide layer.

6. The integrated circuit device as claimed in claim 1 , wherein the gate structure has a metal gate structure including a metal layer.

7. The integrated circuit device as claimed in claim 1 , wherein the gate structure includes a work function control layer, a first gate layer, and a second gate layer sequentially positioned on the gate insulating layer.

8. The integrated circuit device as claimed in claim 1 , wherein the gate spacer structure includes:
a first spacer on opposite side walls of the gate structure, the first spacers including a third dielectric layer having third relative permittivity greater than the first relative permittivity, and having a linear bar shape;
a second spacer on a side wall of the first spacer, on a side wall of the buried dielectric layer, and on the base layer, the second spacer being integral with the buried dielectric layer in an L-shape, and including a same material as the buried dielectric layer;
a third spacer on a side wall and on an upper portion of the second spacer, the third spacer including a same material as the first spacer, and having an L-shape; and
a fourth spacer on a side wall and on an upper portion of the third spacer, the fourth spacer including a same material as the second spacer.

9. The integrated circuit device as claimed in claim 8 , wherein each of the first spacer and the third spacer includes a silicon nitride layer, and each of the buried dielectric layer, the second spacer, and the fourth spacer includes a silicon oxide layer.

10. The integrated circuit device as claimed in claim 1 , wherein the gate spacer structure includes:
a first spacer on both opposite walls of the gate structure, including a third dielectric layer having third relative permittivity greater than the first relative permittivity, and having a linear bar shape;
a second spacer on a side wall of the first spacer and on a side wall of the buried dielectric layer, integral with the buried dielectric layer in a linear bar shape, and including a same material as the buried dielectric layer;
a third spacer on a side wall of the second spacer and on the base layer, including a same material as the first spacer, and having an L-shape; and
a fourth spacer on a side wall and on an upper portion of the third spacer, and including a same material as the second spacer.

11. The integrated circuit device as claimed in claim 10 , wherein each of the first spacer and the third spacer includes a silicon nitride layer, and each of the buried dielectric layer, the second spacer, and the fourth spacer includes a silicon oxide layer.

12. The integrated circuit device as claimed in claim 1 , wherein the gate spacer structure includes:
a first spacer on opposite side walls of the gate structure, including a third dielectric layer having third relative permittivity greater than the first relative permittivity, and having a linear bar shape;
a second spacer on a side wall of the first spacer, on a side wall of the buried dielectric layer, and on the base layer, including a same material as the first spacer, and having an L-shape; and
a third spacer on a side wall and on an upper portion of the second spacer, and including a same material as the buried dielectric layer.

13. The integrated circuit device as claimed in claim 12 , wherein each of the first spacer and the second spacer includes a silicon nitride layer, and each of the buried dielectric layer and the third spacer includes a silicon oxide layer.

14. An integrated circuit device, comprising:
a gate stack structure including:
a gate insulating layer, the gate insulating layer having a first dielectric layer on a base layer and having first relative permittivity, and a second dielectric layer having second relative permittivity greater than the first relative permittivity, and
a gate structure on the gate insulating layer, the gate structure including a metal layer; and

a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including:
a first spacer on opposite side walls of the gate structure, including a third dielectric layer having third relative permittivity greater than the first relative permittivity, and having a linear bar shape,
a second spacer including a buried dielectric layer buried in a recess hole in the first dielectric layer, the second spacer including a same material as the first dielectric layer at a lower portion of the first spacer, on a side wall of the first spacer and a side wall of the buried dielectric layer, integrally disposed with the buried dielectric layer, and including a same material as the buried dielectric layer,
a third spacer on a side wall of the second spacer, including a same material as the first spacer, and having an L shape, and
a fourth spacer on a side wall and an upper portion of the third spacer and including a same material as the second spacer,
wherein a bottom of the first spacer overlaps the gate insulating layer and the buried dielectric layer in the recess hole, such that the gate insulating layer separates the buried dielectric layer in the recess hole from the gate structure.

15. The integrated circuit device as claimed in claim 14 , wherein the second spacer is connected to the buried dielectric layer and is on the base layer so that the second spacer has an L shape, and the third spacer is on the second spacer on the base layer.

16. The integrated circuit device as claimed in claim 14 , wherein the second spacer is on a side wall of the first spacer and on a side wall of the buried dielectric layer in a linear bar shape, and the third spacer is on a side wall of the second spacer and on the base layer.

17. The integrated circuit device as claimed in claim 14 , whe

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Chan-Sic
• Kim Dong-Oh
• Park Je-Min
• Lee Ki-Seok

Classifications

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D84/0147 Primary

  Manufacturing their gate sidewall spacers · CPC title

• H10D64/685 Primary

  being perpendicular to the channel plane · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D30/0278

  forming single crystalline channels on wafers after forming insulating device isolations · CPC title