Dual work function buried gate type transistor and method for fabricating the same

US9704988B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9704988-B2
Application numberUS-201414322671-A
CountryUS
Kind codeB2
Filing dateJul 2, 2014
Priority dateJan 29, 2014
Publication dateJul 11, 2017
Grant dateJul 11, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A transistor may include a source region and a drain region separately formed in a substrate, a trench defined in the substrate between the source region and the drain region, and a buried gate electrode formed. The buried gate electrode includes a high work function liner layer having a bottom portion which is positioned over a bottom of the trench and sidewall portions which are positioned on lower sidewalls of the trench; a low work function liner layer positioned on upper sidewalls of the trench, and overlapping with the source region and the drain region; and a low resistance layer contacting the high work function liner layer and the low work function liner layer, and partially filling the trench.

First claim

Opening claim text (preview).

What is claimed is: 1. A transistor comprising: a source region and a drain region separately formed in a substrate; a trench defined in the substrate between the source region and the drain region; and a buried gate electrode formed in the trench, wherein the buried gate electrode includes: a high work function liner layer having a bottom portion, which is positioned over a bottom of the trench, and sidewall portions, which are positioned on lower sidewalls of the trench; a low work function liner layer positioned on upper sidewalls of the trench, and overlapping with the source region and the drain region; a first barrier layer having vertical and horizontal portions interposed between the high work function liner layer and a first low resistance layer; and a second barrier layer having vertical portions interposed between the low work function liner layer and a second low resistance layer and a horizontal portion interposed between the first and second low resistance layers, wherein the first low resistance layer and the second low resistance layer partially fill the trench. 2. The transistor according to claim 1 , wherein the high work function liner layer and the low work function liner layer include a high work function polysilicon layer and a low work function polysilicon layer, respectively. 3. The transistor according to claim 1 , wherein the high work function liner layer includes a P-type polysilicon layer, and the low work function liner layer includes an N-type polysilicon layer. 4. The transistor according to claim 1 , wherein the first and second low resistance layers includes a metal-containing material, which has a specific resistance lower than the high work function liner layer and the low work function liner layer.

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What does patent US9704988B2 cover?
A transistor may include a source region and a drain region separately formed in a substrate, a trench defined in the substrate between the source region and the drain region, and a buried gate electrode formed. The buried gate electrode includes a high work function liner layer having a bottom portion which is positioned over a bottom of the trench and sidewall portions which are positioned on…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H01L29/7827. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).