Profile control of channel structures for semiconductor devices

Patent metadata

Field	Value
Publication number	US-12183797-B2
Application number	US-202117471863-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	May 12, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

The present disclosure describes a semiconductor device having a channel structure with profile control. The semiconductor device includes a fin structure on a substrate. The fin structure includes a bottom portion on the substrate and a top portion including multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around the multiple semiconductor layers and a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the plurality of semiconductor layers. The S/D structure extends into end portions of the multiple semiconductor layers.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a fin structure on a substrate, wherein the fin structure comprises a bottom portion on the substrate and a top portion comprising a plurality of semiconductor layers, and wherein end portions of the plurality of semiconductor layers have a recessed surface;
a gate structure wrapped around the plurality of semiconductor layers; and
a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the recessed surface of the end portions of the plurality of semiconductor layers, wherein the S/D structure extends into the end portions of the plurality of semiconductor layers.

2. The semiconductor device of claim 1 , wherein a ratio of a distance of the S/D structure extending into the plurality of semiconductor layer to a length of the plurality of semiconductor layers at an edge region ranges from about 5% to about 15%.

3. The semiconductor device of claim 1 , further comprising a spacer structure on the fin structure and in contact with sidewalls of the gate structure, wherein the S/D structure extends laterally beyond a sidewall surface of the spacer structure.

4. The semiconductor device of claim 3 , wherein a distance of the S/D structure extending into the plurality of semiconductor layer is less than a width of the spacer structure.

5. The semiconductor device of claim 1 , further comprising a plurality of inner spacer structures between the plurality of semiconductor layers, wherein the S/D structure laterally extends beyond sidewall surfaces of the plurality of inner spacer structures.

6. The semiconductor device of claim 1 , wherein each of the end portions of the plurality of semiconductor layers has a V shape from a top-down view comprising a sloped recessed center region and an edge region, and wherein the S/D structure extends into the sloped recessed center region.

7. The semiconductor device of claim 1 , wherein each of the end portions of the plurality of semiconductor layers has a sigma (Σ) shape from a top-down view comprising a center region, an edge region, and a recessed intermediate region between the center region and the edge region, and wherein the S/D structure extends into the recessed intermediate region.

8. The semiconductor device of claim 1 , wherein each of the end portions of the plurality of semiconductor layers has a pi (Π) shape from a top-down vie\v comprising a flat recessed center region and an edge region, and wherein the S/D structure extends into the flat recessed center region.

9. A semiconductor device, comprising:
a fin structure on a substrate, wherein the fin structure comprises a plurality of semiconductor layers;
a gate structure wrapped around each of the plurality of semiconductor layers;
a spacer structure on the fin structure and in contact with sidewalls of the gate structure; and
first and second S/D structures on opposite ends of the plurality of semiconductor layers, wherein the first and second S/D structures laterally extends below the spacer structure, and wherein a distance between the first and second S/D structures at a center region of the plurality of semiconductor layers is less than a length of the plurality of semiconductor layers at an edge region.

10. The semiconductor device of claim 9 , wherein a ratio of the distance between the first and second S/D structures to the length of the plurality of semiconductor layers at the edge region ranges from about 70% to about 95%.

11. The semiconductor device of claim 9 , wherein a width of the gate structure is less than the length of the plurality of semiconductor layers at the edge region.

12. The semiconductor device of claim 9 , wherein a distance of the first and second S/D structures laterally extending below the spacer structure is less than a width of the spacer structure.

13. The semiconductor device of claim 9 , further comprising a plurality of inner spacer structures between the gate structure and the first and second S/D structures, wherein the first and second S/D structures laterally extend beyond sidewall surfaces of the plurality of inner spacer structures.

14. The semiconductor device of claim 9 , wherein each of end portions of the plurality of semiconductor layers has a V shape, a sigma shape, or a pi (Π) shape from a top-down view, wherein each of the V, Σ, and Π shapes comprises a recessed region, and wherein the first and second S/D structures extend into the recessed region of the plurality of semiconductor layers.

15. A semiconductor device, comprising:
a plurality of semiconductor layers on a substrate, wherein:
each of the plurality of semiconductor layers comprises a center region and an edge region;
the center region has a first length; and
the edge region has a second length greater than the first length;

a gate structure in contact with the edge region and wrapped around the edge region of the plurality of semiconductor layers; and
a source/drain (S/D) structure adjacent to end portions of the plurality of semiconductor layers, wherein the S/D structure is in contact with the center region and the end region of the plurality of semiconductor layers.

16. The semiconductor device of claim 15 , wherein a ratio of the first length to the second length ranges from about 70% to about 95%.

17. The semiconductor device of claim 15 , wherein a width of the gate structure is less than the second length.

18. The semiconductor device of claim 15 , further comprising a spacer structure above the plurality of semiconductor layers and on a sidewall of the gate structure, wherein a distance of the S/D structure laterally extends below the spacer structure is less than a width of the spacer structure.

19. The semiconductor device of claim 15 , further comprising a plurality of inner spacer structures between the gate structure and the S/D structure, wherein the S/D structure laterally extends towards the plurality of semiconductor layers beyond sidewall surfaces of the plurality of inner spacer structures.

20. The semiconductor device of claim 15 , wherein:
each of the end portions of the plurality of semiconductor layers has a V shape, a sigma (Σ) shape, or a pi (Π) shape from a top-down view;
each of the V, Σ, and Π shapes comprises a recessed region; and
the S/D structure extends into the recessed region of the plurality of semiconductor layers.

Assignees

• Taiwan Semicondcutor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Chao-Wei

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P70/20 Primary

  Cleaning during device manufacture · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title