Semiconductor package

Patent metadata

Field	Value
Publication number	US-12094817-B2
Application number	US-202318125529-A
Country	US
Kind code	B2
Filing date	Mar 23, 2023
Priority date	Jan 3, 2020
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip having a connection pad connected to the first redistribution layer; a vertical connection conductor electrically connected to the connection pad by the first redistribution layer; a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor; an encapsulant filling the first and second through-holes; and a redistribution member including a second redistribution layer. The vertical connection conductor and the core member include a same material. A width of a lower surface of the vertical connection conductor is wider than that of an upper surface thereof, a width of a lower end of the first through-hole is narrower than that of an upper end thereof, and a width of a lower end of the second through-hole is narrower than that of an upper end thereof.

First claim

What is claimed is:

1. A semiconductor package comprising:
a redistribution substrate including a first redistribution layer;
a semiconductor chip on the redistribution substrate and having a connection pads electrically connected to the first redistribution layer;
a plurality of vertical connection conductors disposed around the semiconductor chip, the plurality of vertical connection conductors being electrically connected to the connection pads by the first redistribution layer;
a core member on the redistribution substrate, the core member continuously extending between the semiconductor chip and the plurality of vertical connection conductors, and the core member defining a first through-hole surrounding a side surface of the semiconductor chip, and a plurality of second through-holes surrounding side surfaces of the plurality of vertical connection conductors, respectively;
an encapsulant on the redistribution substrate, covering the semiconductor chip and the plurality of vertical connection conductors; and
a redistribution member on the encapsulant, and including a second redistribution layer electrically connected to the plurality of vertical connection conductors,
wherein the first redistribution layer includes a first signal pattern, a first power pattern, and a first ground pattern,
wherein the core member is electrically connected to the first ground pattern of the first redistribution layer,
wherein the plurality of vertical connection conductors each comprise a plurality of connecting metal layers including different metals,
wherein the core member comprises a plurality of core metal layers including different metals, and
wherein any one of the plurality of connecting metal layers comprises a same metal as any one of the plurality of core metal layers disposed at a same level.

2. The semiconductor package according to claim 1 , wherein the second redistribution layer includes a second signal pattern, a second power pattern, and a second ground pattern, and
wherein at least one of the plurality of vertical connection conductors is electrically connected to the second redistribution layer.

3. The semiconductor package according to claim 1 , wherein the plurality of vertical connection conductors are insulated from the core member.

4. The semiconductor package according to claim 1 , wherein each of the plurality of vertical connection conductors has a vertical cross-sectional shape in which the side surface of each of the plurality of vertical connection conductors is tapered.

5. The semiconductor package according to claim 1 , wherein each of the plurality of vertical connection conductors has a vertical cross-sectional shape in which the side surface of each of the plurality of vertical connection conductors is concave.

6. The semiconductor package according to claim 1 , wherein lower surfaces of the plurality of vertical connection conductors, a lower surface of the core member, and a lower surface of the encapsulant are coplanar with each other.

7. The semiconductor package according to claim 6 , wherein the redistribution substrate further comprises a first insulating layer covering the lower surfaces of the plurality of vertical connection conductors, and a first redistribution via passing through the first insulating layer to connect the first redistribution layer and the lower surfaces of the plurality of vertical connection conductors.

8. The semiconductor package according to claim 1 , wherein upper surfaces of the plurality of vertical connection conductors and an upper surface of the core member are on a higher level than an upper surface of the semiconductor chip.

9. The semiconductor package according to claim 8 , wherein an upper surface of the encapsulant is on a higher level than the upper surfaces of the plurality of vertical connection conductors and the upper surface of the core member.

10. The semiconductor package according to claim 1 , wherein a width of an upper portion of the first through-hole is greater than a width of a lower portion of the first through-hole.

11. The semiconductor package according to claim 1 , wherein a width of an upper portion of each of the plurality of second through-holes is greater than a width of a lower portion of each of the plurality of second through-holes.

12. The semiconductor package according to claim 1 , wherein a width of an upper portion of each of the plurality of vertical connection conductors is smaller than a width of a lower portion of each of the plurality of vertical connection conductors.

13. The semiconductor package according to claim 1 , wherein, on a plane, each of the plurality of vertical connection conductors has a circular shape, and
each of the plurality of second through-holes has a circular shape.

14. The semiconductor package according to claim 1 , wherein, on a plane, each of the plurality of vertical connection conductors has a rectangular shape, and
each of the plurality of second through-holes has a rectangular shape.

15. The semiconductor package according to claim 1 , wherein the core member has a thickness greater than or equal to a thickness of the semiconductor chip.

16. A semiconductor package comprising:
a redistribution substrate including a first redistribution layer;
a semiconductor chip on the redistribution substrate and having connection pads electrically connected to the first redistribution layer;
a plurality of vertical connection conductors around the semiconductor chip, the plurality of vertical connection conductors being electrically connected to the connection pads by the first redistribution layer;
a core member continuously extending between the semiconductor chip and the plurality of vertical connection conductors;
an encapsulant on the redistribution substrate, covering the semiconductor chip and the plurality of vertical connection conductors; and
a redistribution member on the encapsulant, and including a second redistribution layer electrically connected to the plurality of vertical connection conductors,
wherein the first redistribution layer includes a signal pattern, a power pattern, and a ground pattern,
wherein the core member is electrically connected to at least one of the connection pads of the semiconductor chip and to the ground pattern of the first redistribution layer,
wherein the plurality of vertical connection conductors each comprise a plurality of connecting metal layers including different metals,
wherein the core member comprises a plurality of core metal layers including different metals, and
wherein any one of the plurality of connecting metal layers comprises a same metal as any one of the plurality of core metal layers disposed at a same level.

17. The semiconductor package according to claim 16 , wherein the plurality of vertical connection conductors are electrically connected to at least one of the connection pads of the semiconductor chip through the signal pattern of the first redistribution layer.

18. The semiconductor package according to claim 16 , wherein the connection pads of the semiconductor chip are electrically connected to at least one of the signal pattern, the power pattern, and the ground pattern of the first redistribution layer.

19. A semiconductor package comprising:
a redistribution substrate including a redistribution layer;
a semiconductor chip on the redistribution substrate and having connection pads electrically connected to the redistribution layer;
a plurality of vertical connection conductors around the semiconductor chip, the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myungsam
• Ko Youngchan
• Mun Kyungdon

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/354

  comprising polymers · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title