Interposer, semiconductor package structure, and semiconductor process

Patent metadata

Field	Value
Publication number	US-10388598-B2
Application number	US-201715818337-A
Country	US
Kind code	B2
Filing date	Nov 20, 2017
Priority date	Jun 9, 2016
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A semiconductor process includes: (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space; and (c) forming a redistribution layer on the metal layer, wherein the redistribution layer is electrically connected to the at least one metal via.

First claim

What is claimed is:

1. A semiconductor process, comprising:
(a) attaching a metal layer on a carrier;
(b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space;
(c) forming a first redistribution layer on a first surface of the metal layer, wherein the first redistribution layer is electrically connected to the at least one metal via;
(d) attaching a semiconductor die on the first redistribution layer;
(e) separating the carrier from the metal layer;
(f) forming a second redistribution layer on a second surface of the metal layer; and
(g) forming at least one external connection element on the second redistribution layer.

2. The semiconductor process of claim 1 , wherein in (a), the metal layer is adhered to the carrier, and in (b) the portion of the metal layer is removed by etching.

3. The semiconductor process of claim 1 , wherein in (b), the at least one metal via tapers.

4. The semiconductor process of claim 1 , wherein in (b), the at least one metal via disposed in the through hole is a single metal via disposed in the through hole, and the space has a ring shape from a top view and surrounds the metal via.

5. The semiconductor process of claim 1 , wherein in (b), the at least one metal via disposed in the through hole is a plurality of metal vias disposed in the through hole, and the metal vias are spaced apart from each other.

6. The semiconductor process of claim 1 , wherein in (b), the metal via curves inward towards a first surface of the metal via and curves inward or outward towards a second surface of the metal via, the second surface of the metal via being opposite to the first surface of the metal via.

7. The semiconductor process of claim 1 , wherein after (b), the semiconductor process further comprises:
(b 1) filling an isolation material in the space.

8. The semiconductor process of claim 7 , wherein in (b 1), a first surface of the isolation material is substantially coplanar with the first surface of the metal layer, and a second surface of the isolation material is substantially coplanar with the second surface of the metal layer.

9. The semiconductor process of claim 1 , wherein in (c), the first redistribution layer is further electrically connected to the metal layer.

10. The semiconductor process of claim 1 , wherein forming the first redistribution layer in (c) includes forming an insulation layer on the metal layer, the insulation layer extending into the space to form an isolation material between the at least one metal via and the side wall of the through hole.

11. The semiconductor process of claim 10 , wherein in (c), a first surface of the isolation material is substantially coplanar with the first surface of the metal layer, and a second surface of the isolation material is substantially coplanar with the second surface of the metal layer.

12. The semiconductor process of claim 1 , wherein after (d), the semiconductor process further comprises:
(d 1) forming an encapsulant on the first redistribution layer to cover the semiconductor die.

13. The semiconductor process of claim 1 , wherein in (f), the first redistribution layer is electrically connected to the second redistribution layer through the at least one metal via.

14. The semiconductor process of claim 13 , wherein in (f), the second redistribution layer is further electrically connected to the metal layer.

15. A semiconductor process, comprising:
(a) attaching a metal layer on a carrier;
(b) removing a portion of the metal layer to form a through hole and at least one metal via, wherein the at least one metal via is disposed in the through hole, and the at least one metal via is separated from a side wall of the through hole by a space;
(c) forming a first redistribution layer on a first surface of the metal layer, wherein the first redistribution layer is electrically connected to the at least one metal via;
(d) forming a second redistribution layer on a second surface of the metal layer;
(e) attaching a supporting structure on the second redistribution layer;
(f) separating the carrier from the metal layer;
(g) attaching a semiconductor die on the first redistribution layer; and
(h) separating the supporting structure from the second redistribution layer.

16. The semiconductor process of claim 15 , wherein in (d), the first redistribution layer is electrically connected to the second redistribution layer through the at least one metal via.

17. The semiconductor process of claim 16 , wherein in (d), the second redistribution layer is further electrically connected to the metal layer.

18. The semiconductor process of claim 15 , wherein after (d), the semiconductor process further comprises:
(d 1) forming at least one external connection element on the second redistribution layer, and wherein in (e), the supporting structure covers the external connection element.

19. The semiconductor process of claim 15 , wherein after (g), the semiconductor process further comprises:
(g 1) forming an encapsulant on the first redistribution layer to cover the semiconductor die.

Assignees

• Advanced Semiconductor Eng

Inventors

• Lu wen-long
• Huang Min Lung

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title