Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint

Patent metadata

Field	Value
Publication number	US-9269595-B2
Application number	US-201213403859-A
Country	US
Kind code	B2
Filing date	Feb 23, 2012
Priority date	Jan 29, 2010
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.

First claim

What is claimed:

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of first semiconductor die;
mounting a second semiconductor die to the first semiconductor die;
depositing an encapsulant over the first and second semiconductor die;
removing a portion of a surface of the second semiconductor die;
forming a via through the encapsulant over a footprint of the first semiconductor die and extending to the first semiconductor die after removing the portion of the surface of the second semiconductor die;
forming a conductive material in the via to form a conductive pillar extending to through the encapsulant to the first semiconductor die;
forming a build-up interconnect structure including an insulating layer and a redistribution layer each in direct contact with the encapsulant and second semiconductor die, the redistribution layer formed in direct contact with the conductive pillar; and
removing a portion of a surface of the first semiconductor die after forming the build-up interconnect structure.

2. The method of claim 1 , further including removing the portion of the surface of the first semiconductor die and portion of the surface of the second semiconductor die while the second semiconductor die is mounted to the first semiconductor die.

3. The method of claim 1 , further including forming a conductive via through the first semiconductor die.

4. The method of claim 3 , further including forming the build-up interconnect structure comprising an integrated passive device within the build-up interconnect structure.

5. The method of claim 1 , further including:
forming a groove in the semiconductor wafer between the first semiconductor die; and
depositing the encapsulant within the groove.

6. The method of claim 1 , further including disposing a third semiconductor die over the first semiconductor die.

7. The method of claim 1 , further including disposing a discrete semiconductor component over the first semiconductor die.

8. A method of manufacturing a semiconductor device, comprising:
providing a first semiconductor die;
disposing a second semiconductor die over the first semiconductor die;
forming a first bump between the first and second semiconductor die to directly contact the first and second semiconductor die;
disposing a lead frame over the first and second semiconductor die, the lead frame including a plate and conductive bodies extending from the plate to the first semiconductor die;
forming an encapsulant around the conductive bodies of the lead frame;
removing the plate of the lead frame and a portion of a surface of the second semiconductor die;
removing a portion of a surface of the first semiconductor die; and
forming an interconnect structure including an insulating layer and a conductive layer each directly on the second semiconductor die and encapsulant.

9. The method of claim 8 , further including removing the portion of the surface of the first semiconductor die and the portion of the surface of the second semiconductor die after forming the encapsulant over the first semiconductor die and around the second semiconductor die.

10. The method of claim 8 , further including disposing a third semiconductor die over the first semiconductor die.

11. The method of claim 8 ,
wherein removing the plate of the lead frame further includes exposing a portion of the conductive bodies.

12. The method of claim 11 , wherein the conductive bodies form a vertical interconnect structure extending through the encapsulant.

13. The method of claim 8 , further including forming a heat sink or shielding layer on the first semiconductor die.

14. A method of manufacturing a semiconductor device, comprising:
providing a first semiconductor die;
disposing a second semiconductor die over the first semiconductor die;
forming a plurality of discrete interconnect structures over the first semiconductor die to directly connect the first and second semiconductor die;
forming a vertical interconnect structure over the first semiconductor die and adjacent to the second semiconductor die;
depositing an encapsulant over the vertical interconnect structure and first semiconductor die;
removing a portion of a surface of the second semiconductor die, encapsulant, and vertical interconnect structure;
forming an interconnect structure on the second semiconductor die, encapsulant, and vertical interconnect structure; and
removing a portion of a surface of the first semiconductor die after forming the interconnect structure.

15. The method of claim 14 , further including removing the portion of the surface of the second semiconductor die while the second semiconductor die is disposed over the first semiconductor die.

16. The method of claim 15 , further including removing the portion of the surface of the first semiconductor die while the second semiconductor die is disposed over the first semiconductor die.

17. The method of claim 14 , further including disposing a third semiconductor die over and electrically connected to the vertical interconnect structure.

18. The method of claim 14 , further including forming the vertical interconnect structure including forming a bump, microbump, stud bump, post, or conductive pillar.

19. The method of claim 14 , further including forming a conductive via through the first semiconductor die.

20. A method of manufacturing a semiconductor device, comprising:
providing a first semiconductor die;
mounting a second semiconductor die to the first semiconductor die;
forming a vertical interconnect structure over the first semiconductor die;
removing a portion of the second semiconductor die and vertical interconnect structure;
removing a portion of the first semiconductor die; and
forming an interconnect structure including an insulating layer and a redistribution layer each on the second semiconductor die.

21. The method of claim 20 , further including:
forming the vertical interconnect structure and adjacent to the second semiconductor die; and
forming an encapsulant over and around the vertical interconnect structure.

22. The method of claim 21 , further including removing a portion of the encapsulant to expose the vertical interconnect structure.

23. The method of claim 21 , wherein forming the vertical interconnect structure further includes forming a bump, post, or conductive pillar.

24. The method of claim 20 , further including forming a heat sink or shielding layer over the first semiconductor die.

Assignees

• Chi Heejo
• Cho Namju
• Shin Hangil
• Stats Chippac Ltd

Inventors

• Chi Heejo
• Cho Namju
• Shin Hangil

Classifications

• H10W42/284

  shielding resins · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title