Conductive structure and wiring structure including the same

Patent metadata

Field	Value
Publication number	US-10903169-B2
Application number	US-201916399907-A
Country	US
Kind code	B2
Filing date	Apr 30, 2019
Priority date	Apr 30, 2019
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.

First claim

What is claimed is:

1. A wiring structure, comprising:
an upper conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
a lower conductive structure including:
a core portion defining a cavity;
a plurality of electronic devices disposed in the cavity of the core portion; and
a filling material disposed between the electronic devices and a sidewall of the cavity of the core portion; and

an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure through at least one upper through via extending through the upper conductive structure and the intermediate layer.

2. The wiring structure of claim 1 , wherein the cavity extends through the core portion.

3. The wiring structure of claim 1 , wherein the core portion includes a plurality of interconnection vias surrounding the cavity and extending through the core portion.

4. The wiring structure of claim 1 , wherein each of the electronic devices includes at least one electrical contact exposed from the filling material.

5. The wiring structure of claim 1 , wherein the electronic devices are known good electronic devices.

6. The wiring structure of claim 1 , further comprising an encapsulant encapsulating the electronic devices to form a module, and the filling material is disposed between a lateral surface of the module and the sidewall of the cavity of the core portion.

7. The wiring structure of claim 6 , wherein a ratio of a thickness of the module to a gap between the lateral surface of the module and the sidewall of the cavity of the core portion is greater than 10:1.

8. The wiring structure of claim 1 , wherein a ratio of a thickness of the electronic device to a gap between a lateral surface of the electronic device and the sidewall of the cavity of the core portion is greater than 10:1.

9. The wiring structure of claim 1 , wherein the filling material is formed from an ink.

10. The wiring structure of claim 1 , further comprising at least one lower dielectric layer and at least one lower circuit layer, wherein the at least one lower dielectric layer is disposed on a lower surface of the core portion, and the at least one lower circuit layer is disposed on the at least one lower dielectric layer and is electrically connected to the electronic devices.

11. The wiring structure of claim 10 , wherein the upper through via contacts a respective one of a plurality of top electrical contacts of the electronic devices.

12. The wiring structure of claim 1 , further comprising at least one upper dielectric layer and at least one upper circuit layer, wherein the at least one upper dielectric layer is disposed on a upper surface of the core portion, and the at least one upper circuit layer is disposed on the at least one upper dielectric layer and is electrically connected to the electronic devices.

13. The wiring structure of claim 12 , wherein the upper through via contacts a portion of the topmost circuit layer of the lower conductive structure.

14. The wiring structure of claim 12 , wherein the upper circuit layer is electrically connected to the electronic devices through a plurality of upper interconnection vias.

15. The wiring structure of claim 1 , wherein the upper conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of inner vias disposed between two adjacent circuit layers for electrically connecting the two circuit layers, wherein a tapering direction of the inner via of the upper conductive structure is different from a tapering direction of the upper through via.

16. The wiring structure of claim 1 , wherein a length of the upper through via is greater than a thickness of the upper conductive structure.

17. The wiring structure of claim 1 , wherein the electronic devices are electrically connected to the lower conductive structure through both an upper side and a lower side of the electronic devices.

18. A wiring structure, comprising:
an upper conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
a lower conductive structure including:
a core portion defining a cavity;
a module disposed in the cavity of the core portion, wherein the module includes a plurality of known good electronic devices and an encapsulant encapsulating the known good electronic devices; and
a filling material disposed between a lateral surface of the module and a sidewall of the cavity of the core portion; and

an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure through at least one upper through via extending through the upper conductive structure and the intermediate layer.

19. The wiring structure of claim 18 , wherein the core portion includes a plurality of interconnection vias surrounding the cavity and extending through the core portion.

20. The wiring structure of claim 18 , wherein each of the electronic devices includes at least one electrical contact exposed from the encapsulant and the filling material.

21. The wiring structure of claim 18 , wherein a material of the encapsulant is different from a material of the filling material.

22. The wiring structure of claim 18 , wherein a ratio of a thickness of the module to a gap between the lateral surface of the module and the sidewall of the cavity of the core portion is greater than 10:1.

23. A wiring structure, comprising:
a high-density conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
a low-density conductive structure including:
a core portion defining a cavity;
a plurality of electronic devices disposed in the cavity of the core portion; and
a filling material disposed between the electronic devices and a sidewall of the cavity of the core portion; and

an intermediate layer disposed between the high-density conductive structure and the low-density conductive structure and bonding the high-density conductive structure and the low-density conductive structure together, wherein the high-density conductive structure is electrically connected to the low-density conductive structure through at least one upper through via extending through the high-density conductive structure and the intermediate layer.

24. The wiring structure of claim 23 , wherein a line space of a circuit layer of the low-density conductive structure is greater than a line space of the circuit layer of the high-density conductive structure.

25. The wiring structure of claim 23 , wherein the low-density conductive structure further includes at least one lower dielectric layer and at least one lower circuit layer, wherein the at least one lower dielectric layer is disposed on a lower surface of the core portion, and the at least one lower circuit layer is disposed on the at least one lower dielectric layer and is electrically connected to the electronic devices; and th

Assignees

• Advanced Semiconductor Eng

Inventors

• Huang Wen Hung

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W72/071

  Connecting or disconnecting · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title