Semiconductor device with tiered pillar and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10256114-B2
Application number	US-201715467794-A
Country	US
Kind code	B2
Filing date	Mar 23, 2017
Priority date	Mar 23, 2017
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
electrically connecting a semiconductor die to an interposer, the semiconductor die having a top surface, a bottom surface, and one or more side surfaces adjoining the top surface to the bottom surface;
forming a first tier of a conductive pillar such that the first tier is peripherally beyond the one or more side surfaces of the semiconductor die and the first tier is electrically connected to the interposer, wherein said forming the first tier comprises:
forming a first layer over the interposer;
forming a first hole through the first layer to expose the interposer; and
filling the first hole with conductive material to form the first tier electrically connected to the interposer; and

forming a second tier of the conductive pillar such that the second tier is on and electrically connected to the first tier of the conductive pillar, wherein said forming the second tier comprises:
forming a second layer over the first layer and the first tier;
forming a second hole through the second layer and over the first tier to expose the first tier; and
filling the second hole with conductive material to form the second tier electrically connected to the first tier.

2. The method of claim 1 , further comprising forming another interposer on and electrically connected to the second tier of the conductive pillar.

3. The method of claim 2 , further comprising electrically attaching another semiconductor device to the other interposer.

4. The method of claim 1 , further comprising forming a conductive interconnection structure on the interposer.

5. The method of claim 1 , wherein said electrically connecting the semiconductor die to the interposer comprises attaching micro bumps of the semiconductor to micro pads of the interposer.

6. The method of claim 5 , further comprising filling a region between the bottom surface of the semiconductor die and the interposer with an underfill material.

7. The method of claim 1 , wherein:
said forming the first hole comprises forming the first hole with a first width; and
said forming the second hole comprises forming the second hole with a second width that is smaller than the first width.

8. A method of manufacturing a semiconductor device, the method comprising:
electrically connecting a semiconductor die to one or more first redistribution layers, the semiconductor die having a top surface, a bottom surface, and one or more side surfaces adjoining the top surface to the bottom surface;
forming a first tier of a conductive pillar such that the first tier is peripherally beyond the one or more side surfaces of the semiconductor die and the first tier is electrically connected to the one or more first redistribution layers;
forming a second tier of the conductive pillar such that the second tier is on and electrically connected to the first tier of the conductive pillar; and
forming one or more second redistribution layers over the top surface of the semiconductor die and electrically connected to the second tier of the conductive pillar.

9. The method of claim 8 , further comprising forming a plurality conductive interconnection structures that are electronically connected to the one or more first redistribution layers.

10. The method of claim 8 , wherein said forming the first tier comprises:
forming a first layer over the one or more first redistribution layers;
forming a first hole through the first layer to expose the one or more first redistribution layers; and
filling the first hole with conductive material to form the first tier electrically connected to the one or more first redistribution layers.

11. The method of claim 10 , wherein forming the second tier comprises:
forming a second layer over the first layer and the first tier;
forming a second hole through the second layer and over the first tier to expose the first tier; and
filling the second hole with conductive material to form the second tier electrically connected to the first tier.

12. The method of claim 11 , wherein:
said forming the first hole comprises forming the first hole with a first width; and
said forming the second hole comprises forming the second hole with a second width that is smaller than the first width.

13. A method of manufacturing a semiconductor device, the method comprising:
operatively coupling a plurality of interconnection structures on a bottom surface of a semiconductor die to one or more first redistribution layers; and
forming one or more conductive pillars about a periphery of the semiconductor die and electrically connected to the one or more first redistribution layers, each conductive pillar comprising a plurality of stacked tiers, wherein said forming the one or more conductive pillars comprises forming each conductive pillar of the one or more conductive pillars with an aspect ratio that is greater than or equal to two.

14. The method of claim 13 , further comprising forming one or more second redistribution layers over the semiconductor die and electrically connected to the one or more first redistribution layers via the one or more conductive pillars.

15. The method of claim 13 , wherein said forming the one or more conductive pillars comprises:
forming a first tier of the plurality of stacked tiers directly connected to the one or more first redistribution layers; and
forming a second tier of the plurality of stacked tiers directly on the first tier.

16. The method of claim 15 , wherein said forming the second tier comprises forming the second tier such the second tier has a width that is smaller than a width of the first tier.

Assignees

• Amkor Technology Inc

Inventors

• Huemoeller Ronald Patrick
• Kelly Michael G
• Zwenger Curtis

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title