Semiconductor package

Patent metadata

Field	Value
Publication number	US-11626367-B2
Application number	US-202016988831-A
Country	US
Kind code	B2
Filing date	Aug 10, 2020
Priority date	Jan 3, 2020
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip having a connection pad connected to the first redistribution layer; a vertical connection conductor electrically connected to the connection pad by the first redistribution layer; a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor; an encapsulant filling the first and second through-holes; and a redistribution member including a second redistribution layer. The vertical connection conductor and the core member include a same material. A width of a lower surface of the vertical connection conductor is wider than that of an upper surface thereof, a width of a lower end of the first through-hole is narrower than that of an upper end thereof, and a width of a lower end of the second through-hole is narrower than that of an upper end thereof.

First claim

What is claimed is:

1. A semiconductor package comprising:
a redistribution substrate having a first surface and a second surface, opposing the first surface, the redistribution substrate including a first redistribution layer;
a semiconductor chip disposed on the first surface of the redistribution substrate and having a connection pad disposed on the first surface of the redistribution substrate and connected to the first redistribution layer;
a vertical connection conductor having a lower surface disposed on the first surface of the redistribution substrate, the vertical connection conductor being electrically connected to the connection pad by the first redistribution layer;
a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor;
an encapsulant disposed on the first surface of the redistribution substrate, covering the semiconductor chip and an upper surface of the vertical connection conductor, and filling the first through-hole and the second through-hole; and
a redistribution member disposed on the encapsulant, and including a second insulating layer disposed on the encapsulant, a second redistribution layer disposed on the second insulating layer, and a second redistribution via electrically connecting the second redistribution layer to the vertical connection conductor by penetrating through the second insulating layer,
wherein the vertical connection conductor comprises a plurality of connecting metal layers including different metals,
wherein the core member comprises a plurality of core metal layers including different metals,
wherein any one of the plurality of connecting metal layers comprises a same metal as any one of the plurality of core metal layers disposed at a same level,
a width of the lower surface of the vertical connection conductor is wider than a width of the upper surface of the vertical connection conductor,
a width of a lower end of the first through-hole is narrower than a width of an upper end of the first through-hole,
a width of a lower end of the second through-hole is narrower than a width of an upper end of the second through-hole,
wherein the encapsulant has a first via hole exposing a portion of the upper surface of the vertical connection conductor, and a width of the first via hole is narrower than the width of the upper surface of the vertical connection conductor,
the second insulating layer fills the first via hole, and has a second via hole exposing a portion of the upper surface of the vertical connection conductor exposed from the encapsulant by the first via hole, and
the second redistribution via is disposed in the second via hole, and is spaced apart from a side wall surface of the first via hole.

2. The semiconductor package according to claim 1 , wherein the vertical connection conductor and the core member are insulated from each other by the encapsulant.

3. The semiconductor package according to claim 1 , wherein the vertical connection conductor has a vertical cross-sectional shape in which a side surface of the vertical connection conductor is tapered,
the first through-hole has a vertical cross-sectional shape in which a first side wall surface of the first through-hole is tapered, and
the second through-hole has a vertical cross-sectional shape in which a second side wall surface of the second through-hole is tapered.

4. The semiconductor package according to claim 1 , wherein the vertical connection conductor has a vertical cross-sectional shape in which a side surface of the vertical connection conductor is concave,
the first through-hole has a vertical cross-sectional shape in which a first side wall surface of the first through-hole is convex, and
the second through-hole has a vertical cross-sectional shape in which a second side wall surface of the second through-hole is convex.

5. The semiconductor package according to claim 1 , wherein the core member has a vertical cross-sectional shape in which an outer side surface is tapered.

6. The semiconductor package according to claim 5 , wherein the encapsulant covers the outer side surface of the core member.

7. The semiconductor package according to claim 1 , wherein the lower surface of the vertical connection conductor, a lower surface of the core member, and a lower surface of the encapsulant are on a same plane, and
the redistribution substrate comprises first insulating layer on the same plane, the first redistribution layer on the first insulating layer, and a first redistribution via passing through the first insulating layer to connect the first redistribution layer and the vertical connection conductor.

8. The semiconductor package according to claim 1 , wherein the upper surface of the vertical connection conductor and an upper surface of the core member are on a higher level than an upper surface of the semiconductor chip, and
an upper surface of the encapsulant is on a higher level than the upper surface of the vertical connection conductor and the upper surface of the core member.

9. The semiconductor package according to claim 8 ,
wherein the side wall surface of the first via hole and a side wall surface of the second via hole are spaced apart from each other.

10. The semiconductor package according to claim 1 , wherein the vertical connection conductor is provided as a plurality of vertical connection conductors spaced apart from each other, and the second through-hole is provided as a plurality of second through-holes that are spaced apart from each other, and
wherein the plurality of second through-holes respectively accommodate the plurality of vertical connection conductors.

11. The semiconductor package according to claim 1 , wherein the vertical connection conductor is provided as a plurality of vertical connection conductors spaced apart from each other, and the second through-hole is provided as a plurality of second through-holes that are spaced apart from each other, and
wherein the plurality of second through-holes respectively accommodate the plurality of vertical connection conductors, and
wherein at least a portion of the plurality of second through-holes are connected to each other.

12. The semiconductor package according to claim 1 , wherein the core member has a plate shape having a thickness greater than or equal to a thickness of the semiconductor chip.

13. The semiconductor package according to claim 1 , further comprising:
a passivation layer disposed on the second surface of the redistribution substrate and having an opening exposing a portion of the first redistribution layer;
an under-bump metal disposed on the opening and electrically connected to the portion of the first redistribution layer; and
a connection bump disposed on the passivation layer and electrically connected to the first redistribution layer by the under-bump metal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myungsam
• Ko Youngchan
• Mun Kyungdon

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/354

  comprising polymers · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title