Hierarchical power management apparatus and method

Patent metadata

Field	Value
Publication number	US-12093100-B2
Application number	US-202017033753-A
Country	US
Kind code	B2
Filing date	Sep 26, 2020
Priority date	Sep 26, 2020
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of dies including compute dies and I/O dies;
a plurality of power management units, wherein each die of the plurality includes a power management unit such that at least one of the power management units is a supervisor unit and at least two of the power management units are supervisee units, wherein the power management units are arranged in a hierarchical manner such that the supervisor unit controls the at least two supervisee units; and
a plurality of maximum power detectors to detect a droop in a voltage of an input power supply rail, wherein each maximum power detector is positioned in one of the compute dies, wherein a compute die positioned between at least two compute dies is an owner of decisions associated with a maximum power detector of the compute die.

2. The apparatus of claim 1 , wherein the maximum power detectors in the at least two compute dies are disabled.

3. The apparatus of claim 2 , comprising a plurality of fast droop detectors, wherein each maximum power detector includes a fast droop detector, wherein the fast droop detectors are enabled even when the maximum power detectors are disabled.

4. The apparatus of claim 1 comprising a plurality of fast droop detectors, wherein each compute die of the plurality includes a fast droop detector.

5. The apparatus of claim 4 , wherein the fast droop detector in all compute dies are enabled.

6. The apparatus of claim 1 , wherein a power management unit of one of the I/O dies is the supervisor unit, and wherein the power management units of the compute dies are the supervisee units.

7. The apparatus of claim 1 , wherein the maximum power detector of the compute die is a multi-threshold power detector to detect the droop at multiple thresholds including a fast detect threshold to detect a fast droop in the voltage of the input power supply rail.

8. The apparatus of claim 7 , wherein upon detection of the fast droop, the maximum power detector is to trigger a hard throttle to all processor cores of all the compute dies.

9. The apparatus of claim 8 comprising:
a first interconnect fabric coupled to the supervisor unit and the supervisee units; and
a second interconnect fabric coupled to the supervisor unit and the supervisee units, wherein the second interconnect fabric is faster than the first interconnect fabric, and wherein the hard throttle is sent via the second interconnect fabric.

10. The apparatus of claim 8 , wherein the hard throttle comprises reduction in an operating voltage and/or frequency of all the compute dies within a predetermined time, thereafter the supervisor unit to send a global shared frequency ceiling for all the supervisee units within a domain of the supervisor unit.

11. The apparatus of claim 10 , wherein the supervisee units to send a message to the supervisor unit indicative of the global shared frequency ceiling, and wherein the supervisee units to enforce the global shared frequency ceiling within their respective dies.

12. The apparatus of claim 11 , wherein the compute die, which is the owner of decisions associated with the maximum power detector of the compute die, is to de-assert the hard throttle after the compute dies indicate to the compute die that the global shared frequency ceiling is enforced and the plurality of compute dies operate at a safe power level.

13. The apparatus of claim 12 , wherein the supervisor unit is to gradually increase the global shared frequency ceiling for compute dies after a predetermined wait time expires from a time the hard throttle is de-asserted.

14. The apparatus of claim 7 , wherein upon detection that the voltage of the droop crossed one or more of the multiple thresholds while the voltage of the droop does not cross the fast detect threshold, the maximum power detector is to trigger a soft throttle to all processor cores of all the compute dies.

15. The apparatus of claim 14 , wherein the soft throttle comprises stretching a duty cycle of one or more clocks to all processor cores of the compute die.

Assignees

• Intel Corp

Inventors

• Garg Vivek
• Varma Ankush
• Sistla Krishnakanth
• Gupta Nikhil
• Baligar Nikethan Shivanand
• Wang Stephen
• Palit Nilanjan
• Kam Timothy Yee-Kwong
• Purandare Adwait
• Gupta Ujjwal
• Chen Stanley
• Shapira Dorit
• Venugopal Shruthi
• Chemudupati Suresh
• Parikh Rupal
• Dehaemer Eric
• Sampath Pavithra
• Kandula Phani Kumar
• Bansal Yogesh
• Mulla Dean
• Tulanowski Michael
• Haake Stephen Paul
• Herdrich Andrew
• Das Ripan
• Haider Nazar Syed
• Sewani Aman

Classifications

• G06F2213/40

  Bus coupling · CPC title

• G06F13/20

  for access to input/output bus · CPC title

• G06F1/30

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/324

  by lowering clock frequency · CPC title