System and method for managing power in a chip multiprocessor using a proportional feedback mechanism

Patent metadata

Field	Value
Publication number	US-9507405-B2
Application number	US-201414308079-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Jun 18, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A system includes a power management unit that may monitor the power consumed by a processor including a plurality of processor core. The power management unit may throttle or reduce the operating frequency of the processor cores by applying a number of throttle events in response to determining that the plurality of cores is operating above a predetermined power threshold during a given monitoring cycle. The number of throttle events may be based upon a relative priority of each of the plurality of processor cores to one another and an amount that the processor is operating above the predetermined power threshold. The number of throttle events may correspond to a portion of a total number of throttle events, and which may be dynamically determined during operation based upon a proportionality constant and the difference between the total power consumed by the processor and a predetermined power threshold.

First claim

What is claimed is:

1. A system comprising:
a processor having a plurality of processor cores, each configured to execute program instructions; and
a power management unit coupled to the plurality of processor cores and configured to throttle each of a subset of the plurality of processor cores by a number of throttle events in response to determining that the processor is operating above a predetermined power threshold during a given monitoring cycle;
wherein the number of throttle events is based upon a relative priority of each of the plurality of processor cores to one another and an amount that the processor is operating above the predetermined power threshold;
wherein the power management unit is further configured to determine the number of throttle events dependent upon a product of a number of throttle events per watt and the difference between the total power consumed by the processor and the predetermined power threshold.

2. The system of claim 1 , wherein the power management unit is further configured to throttle the subset of the plurality of processor cores in a predetermined throttling order.

3. The system of claim 2 , wherein the power management unit is further configured to resume at least some of the subset of the plurality of processor cores by at least some of the number of throttle events and in an order that is opposite the predetermined order in response to determining that the processor is operating below the predetermined power threshold.

4. The system of claim 1 , wherein the power management unit is configured to calculate the amount that the processor is operating above the predetermined power threshold as a difference between a total power consumed by the processor and the predetermined power threshold.

5. The system of claim 1 , wherein the predetermined number of throttle events corresponds to a portion of a total number of throttle events, wherein each throttle event reduces an operating frequency by a predetermined number of clock cycles.

6. The system of claim 5 , wherein the power management unit is configured to distribute the total number of throttle events among each core of the subset of the plurality of processor cores according to a weighted distribution that is based upon the relative priority of each of the plurality of processor cores to one another.

7. The system of claim 1 , wherein the power management unit is configured to distribute more throttle events to processor cores having a lower priority than other processor cores during each given monitoring cycle.

8. The system of claim 1 , wherein the power management unit includes a programmable storage that stores the predetermined power threshold.

9. The system of claim 1 , wherein the power management unit includes a programmable storage that stores the number of throttle events per watt.

10. The system of claim 2 , wherein the power management unit includes a programmable storage that stores the predetermined throttling order.

11. A method comprising:
throttling, by a power management unit, each of a subset of a plurality of processor cores of a processor by a number of throttle events in response to determining that the processor is operating above a predetermined power threshold during a given monitoring cycle;
wherein the number of throttle events is based upon a relative priority of each of the plurality of processor cores to one another and an amount that the processor is operating above the predetermined power threshold; and
multiplying, by the power management unit, a number of throttle events per watt by a difference between the total power consumed by the processor and the predetermined power threshold to dynamically determine during operation, the number of throttle events.

12. The method of claim 11 , further comprising throttling the subset of the plurality of processor cores in a predetermined throttling order.

13. The method of claim 12 , further comprising resuming at least some of the subset of the plurality of processor cores by at least some of the number of throttle events and in an order that is opposite the predetermined order in response to determining that the processor is operating below the predetermined power threshold.

14. The method of claim 11 , further comprising subtracting, by the power management unit, the predetermined power threshold from a total power consumed by the processor to calculate the amount that the processor is operating above the predetermined power threshold.

15. The method of claim 11 , wherein the number of throttle events corresponds to a portion of a total number of throttle events, wherein each throttle event reduces an operating frequency of the processor cores to which it is applied by a predetermined number of clock cycles.

16. The method of claim 11 , further comprising programming a storage to store the number of throttle events per watt.

17. The method of claim 11 , further comprising distributing the number of throttle events among each core of the subset of the plurality of processor cores according to a weighted distribution that is based upon the relative priority of each of the plurality of processor cores to one another, wherein more throttle events are distributed to processor cores having a lower priority than other processor cores during each given monitoring cycle.

18. The method of claim 11 , further comprising programming a storage to store the predetermined power threshold.

Assignees

• Oracle Int Corp

Inventors

• Krishnaswamy Venkatram
• Konstadinidis Georgios K
• Turullols Sebastian
• Yanggong Yifan

Classifications

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title