Dynamically adjusting power of non-core processor circuitry including buffer circuitry

Patent metadata

Field	Value
Publication number	US-9501129-B2
Application number	US-201313780052-A
Country	US
Kind code	B2
Filing date	Feb 28, 2013
Priority date	Sep 28, 2011
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a variable frequency domain including a plurality of cores and a first portion of system agent circuitry separate from the plurality of cores, the first system agent circuitry portion including at least one cache memory, at least one cache controller, a memory coherency agent, an interrupt routing controller and an interconnect structure; and
at least one fixed frequency domain including a power control unit (PCU), a first agent to communicate with one or more off-chip devices, a second agent to communicate off-chip via one or more links and a memory agent, wherein the PCU is to synchronize clock gating a plurality of clocks of the variable frequency domain and maintain alignment with one or more global clocks and thereafter cause a frequency change to the variable frequency domain without draining the first system agent circuitry portion of pending transactions from a plurality of sources including one or more of the plurality of cores, the first agent and the memory agent.

2. The processor of claim 1 , wherein the PCU is to enable a concurrent frequency change to the at least one cache memory and the plurality of cores.

3. The processor of claim 1 , further comprising an uncore logic having a first portion present in the variable frequency domain and a second portion present in the at least one fixed frequency domain.

4. The processor of claim 3 , further comprising an interface comprising a bubble generator buffer to couple the variable frequency domain to a first fixed frequency domain of the processor, wherein the PCU is to drain the interface and to block the interface and to thereafter enable the frequency change to the variable frequency domain.

5. The processor of claim 4 , wherein the PCU is to execute a freeze mode to block the interface during the frequency change, wherein in the freeze mode, the PCU is to prevent the first fixed frequency domain and the variable frequency domain from sending a transaction into the interface.

6. The processor of claim 1 , wherein the variable frequency domain includes a global interconnect to couple a plurality of units of the variable frequency domain and a local interconnect to couple a first unit and a second unit of the plurality of units.

7. The processor of claim 1 , wherein the PCU is to provide a value of a time stamp counter to the variable frequency domain after the frequency change.

8. A non-transitory machine-readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
blocking a first unit in a first frequency domain of a processor from sending transactions to a boundary unit coupled between the first frequency domain and a second frequency domain of the processor, the first unit comprising a last level cache (LLC);
stopping the boundary unit responsive to determining that the boundary unit is empty of transactions; and
gating a plurality of clocks of the first frequency domain on a common clock edge and changing a frequency of the plurality of clocks from a first clock frequency to a second clock frequency while maintaining alignment with one or more global clocks of the processor and maintaining a state of the first frequency domain, without draining the first unit of transactions received from a plurality of sources of the first frequency domain and the second frequency domain, including changing a frequency of the LLC and a core associated with the LLC from the first clock frequency to the second clock frequency.

9. The non-transitory machine-readable medium of claim 8 , wherein the first unit further comprises a system agent unit of the processor.

10. The non-transitory machine-readable medium of claim 8 , wherein the method further comprises sending a block signal from a power control unit (PCU) of the processor to the first unit to block the first unit from sending the transactions to the boundary unit.

11. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises receiving an acknowledgement from the first unit that the first unit has blocked sending the transactions to the boundary unit responsive to the block signal.

12. The non-transitory machine-readable medium of claim 11 , wherein the method further comprises:
quiescing a plurality of cores of the first frequency domain; and
blocking a plurality of interfaces between the first frequency domain and the second frequency domain.

13. The non-transitory machine-readable medium of claim 10 , wherein changing the frequency of the plurality of clocks includes reloading a plurality of phase lock loops (PLLs) from the first clock frequency to the second clock frequency.

14. A system comprising:
a first multicore processor including a plurality of cores and a variable frequency domain having system agent circuitry including home agent circuitry, a shared cache memory, a cache controller, and a power control unit (PCU) including a frequency control logic to cause a frequency of the variable frequency domain to change without draining the variable frequency domain of pending transactions including at least one pending transaction issued from a second multicore processor, stop a plurality of clocks of the variable frequency domain at a common clock edge, and update a frequency of the variable frequency domain while the plurality of clocks are stopped and alignment is maintained between the plurality of clocks and one or more global clocks of the first multicore processor;
the second multicore processor coupled to the first multicore processor; and
a first portion of a system memory coupled to the first multicore processor and a second portion of the system memory coupled to the second multicore processor.

15. The system of claim 14 , wherein the frequency control logic is to block a first unit in the variable frequency domain from sending transactions to a boundary unit coupled between the variable frequency domain and a second frequency domain of the first multicore processor during the frequency change.

16. The system of claim 15 , wherein the frequency control logic is to stop the boundary unit responsive to determining that the boundary unit is empty of transactions and send a block signal to the first unit to block the first unit from sending the transactions to the boundary unit and receive an acknowledgement from the first unit that the first unit has blocked sending the transactions to the boundary unit responsive to the block signal.

17. The system of claim 16 , wherein the frequency control logic is to quiesce the plurality of cores of the variable frequency domain, and block a plurality of interfaces between the variable frequency domain and the second frequency domain after receipt of acknowledgment of the block signal.

18. The system of claim 14 , wherein the PCU is to provide a value of a time stamp counter to the variable frequency domain after the frequency is updated.

Assignees

• Intel Corp

Inventors

• Sistla Krishnakanth
• Mulla Dean
• Garg Vivek
• Rowland Mark
• Doraiswamy Suresh
• Srinivasa Ganapati
• Gilbert Jeffrey D

Classifications

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title