Core-level dynamic voltage and frequency scaling in a chip multiprocessor

Patent metadata

Field	Value
Publication number	US-9619240-B2
Application number	US-201213811280-A
Country	US
Kind code	B2
Filing date	Feb 4, 2012
Priority date	Feb 4, 2012
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Techniques described herein generally include methods and systems related to manufacturing a chip multiprocessor having multiple processor cores. An example method may include receiving performance or reliability information associated with each of the multiple processor cores, wherein the received performance or reliability information is determined prior to packaging of the chip multiprocessor, and storing the received performance or reliability information such that stored performance or reliability information is used to adjust an operating parameter of at least one of the multiple processor cores of the chip multiprocessor.

First claim

I claim:

1. A method to manufacture a chip multiprocessor having multiple processor cores, the method comprising:
receiving performance or reliability information associated with each of the multiple processor cores, wherein the received performance or reliability information is determined prior to packaging of the chip multiprocessor by testing at least one computing submodule of each of the multiple processor cores; and
storing the received performance or reliability information such that the stored performance or reliability information is used to adjust an operating parameter of at least one processor core of the multiple processor cores of the chip multiprocessor, wherein the performance or reliability information associated with each of the multiple processor cores comprises, for each of the multiple processor cores, frequency vs. power use information for the at least one computing submodule of each of the multiple processor cores.

2. The method of claim 1 , wherein adjusting the operating parameter of the at least one processor core of the multiple processor cores comprises programming a power management unit associated with the chip multiprocessor to optimize power use or clock frequency of the at least one processor core based on the stored performance or reliability information associated with the at least one processor core.

3. The method of claim 2 , wherein one of optimizing power use and clock frequency of the chip multiprocessor comprises assigning tasks to one or more of the multiple processor cores based on the stored performance or reliability information associated with the at least one processor core.

4. The method of claim 1 , wherein adjusting the operating parameter of the at least one processor core comprises adjusting the voltage or frequency provided to one or more of the multiple processor cores by a power management unit.

5. The method of claim 1 , wherein testing the at least one computing submodule comprises testing at least one of: a shifter, an adder, a cache, a bus-processing unit, a network interface, a floating point unit, an arithmetic unit, or a specialty operations unit.

6. The method of claim 1 , wherein the frequency vs. power information for the at least one computing submodule includes frequency slope and intercept for power use for the at least one computing submodule.

7. The method of claim 1 , wherein storing the received performance or reliability information comprises recording the performance or reliability information to an on-chip registry of the chip multiprocessor.

8. The method of claim 1 , wherein storing the received performance or reliability information comprises storing the received performance or reliability information in a database accessible by a power management unit associated with the chip multiprocessor.

9. The method of claim 1 , wherein storing the received performance or reliability information comprises storing the received performance or reliability information for the at least one processor core on the at least one processor core.

10. The method of claim 1 , wherein adjusting the operating parameter of the at least one processor core of the multiple processor cores comprises determining one of a power rating, a frequency, and an operating voltage of the at least one processor core of the multiple processor cores based on the received performance or reliability information associated with the at least one processor core.

11. The method of claim 10 , wherein the power rating comprises one of an average power consumption and a peak power consumption of the at least one processor core.

12. A method to manage frequency and voltage provided to processor cores in a chip multiprocessor, the method comprising:
determining computational requirements for a task to be completed by the chip multiprocessor, the computational requirements being based on make-up of the task; and
based on the determined computational requirements and on stored performance or reliability information associated with each of the processor cores, adjusting an operating parameter of at least one processor core of the processor cores of the chip multiprocessor, wherein the stored performance or reliability information associated with each of the processor cores;
is determined prior to packaging of the chip multiprocessor by testing at least one computing submodule of each of the processor cores, and
comprises, for each of the processor cores, frequency vs. power use information for the at least one computing submodule of each of the processor cores.

13. The method of claim 12 , wherein adjusting the operating parameter of the at least one processor core of the processor cores comprises optimizing power use or clock frequency of the at least one processor core based on the stored performance or reliability information associated with the at least one processor core.

14. The method of claim 13 , wherein one of optimizing power use and clock frequency of the chip multiprocessor comprises assigning tasks to one or more of the processor cores based on the stored performance or reliability information associated with the at least one processor core.

15. The method of claim 14 , wherein assigning the tasks to the one or more of the processor cores comprises assigning the tasks to at least one of a first processor core and a second processor core based on execution instructions contained in the tasks.

16. The method of claim 15 , further comprising weighting a task in categories of instructions performed by each computing submodule of each of the first processor core and the second processor core.

17. The method of claim 12 , wherein the stored performance or reliability information is disposed in an on-chip registry of the chip multiprocessor.

18. The method of claim 12 , further comprising:
based on the stored performance or reliability information associated with the processor cores, selecting a processor core from the processor cores in the chip multiprocessor; and
preventing the processor core from performing the task,
wherein the stored performance or reliability information is determined prior to packaging of the chip multiprocessor.

19. A chip multiprocessor formed on a single die, the chip multiprocessor comprising:
a first processor core formed on the die;
a second processor core formed on the die; and
an on-chip registry formed on the die and configured with performance or reliability information associated with the first processor core and performance or reliability information associated with the second processor core,
wherein the performance or reliability information associated with the first processor core comprises frequency vs. power use information for at least one computing submodule of the first processor core, that is determined by testing the at least one computing submodule of the first processor core prior to packaging of the chip multiprocessor, and the performance or reliability information associated with the second processor core comprises frequency vs. power use information, for at least one computing submodule of the second processor core, that is determined by testing the at least one computing submodule of the second processor core prior to packaging of the chip multiprocessor.

20. The chip multiprocessor of claim 19 , wherein the on-chip registry comprises a registry disposed in the first processor core and a registry disposed in the second processor core.

Assignees

• Kruglick Ezekiel
• Empire Technology Dev Llc

Inventors

• Kruglick Ezekiel

Classifications

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F9/4405 Primary

  Initialisation of multiprocessor systems · CPC title

• Y02B60/1239

  Cross-Sectional Technologies · mapped topic

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title