Semiconductor package

Patent metadata

Field	Value
Publication number	US-12087696-B2
Application number	US-202318095900-A
Country	US
Kind code	B2
Filing date	Jan 11, 2023
Priority date	Dec 24, 2019
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

First claim

What is claimed is:

1. A semiconductor package comprising:
a lower semiconductor device including a first substrate having a first surface, a plurality of first through electrodes each having a first horizontal width, and a plurality of second through electrodes each having a second horizontal width, wherein the plurality of first through electrodes and the plurality of second through electrodes each extend from a lower surface of the lower semiconductor device to the first surface of the first substrate, and the second horizontal width is greater than the first horizontal width; and
an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the plurality of first through electrodes and to the plurality of second through electrodes, the upper semiconductor device configured to receive power through the plurality of second through electrodes.

2. The semiconductor package of claim 1 , wherein the first horizontal width is about 1 μm to about 7 μm and the second horizontal width is about 10 μm to about 20 μm.

3. The semiconductor package of claim 1 , wherein the lower semiconductor device and the upper semiconductor device have a same plane area.

4. The semiconductor package of claim 1 , wherein the first surface faces the upper semiconductor device,
the first substrate includes a second surface opposite to the first surface, and
the lower semiconductor device comprises
a semiconductor device layer arranged on the first surface of the first substrate.

5. The semiconductor package of claim 1 , wherein the first surface faces the upper semiconductor device,
the first substrate includes a second surface opposite to the first surface, and
wherein the lower semiconductor device comprises:
a plurality of first upper pads on the first surface of the first substrate, the plurality of first upper pads electrically connected to the plurality of first through electrodes; and
a plurality of second upper pads on the first surface of the first substrate, the plurality of second upper pads electrically connected to the plurality of second through electrodes, and
wherein a horizontal width of each of the plurality of second upper pads is greater than a horizontal width of each of the plurality of first upper pads.

6. The semiconductor package of claim 5 , wherein the upper semiconductor device comprises:
a second substrate including a lower surface facing the lower semiconductor device;
a plurality of first pads on the lower surface of the second substrate, the plurality of first pads electrically connected to the plurality of first upper pads; and
a plurality of second pads on the lower surface of the second substrate, the plurality of second pads electrically connected to the plurality of second upper pads, and
wherein a horizontal width of each of the plurality of second pads is greater than a horizontal width of each of the plurality of first pads.

7. The semiconductor package of claim 1 , further comprising:
a plurality of first upper connection bumps electrically connecting the upper semiconductor device to the plurality of first through electrodes;
a plurality of second upper connection bumps electrically connecting the upper semiconductor device to the plurality of second through electrodes; and
an insulation adhesive layer between the lower semiconductor device and the upper semiconductor device, the insulation adhesive layer surrounding the plurality of first upper connection bumps and the plurality of second upper connection bumps.

8. The semiconductor package of claim 1 , wherein the plurality of first through electrodes are arranged in a central portion of the lower semiconductor device and the plurality of second through electrodes are arranged in an outer portion of the lower semiconductor device.

9. The semiconductor package of claim 1 , wherein the upper semiconductor device is configured to generate an amount of heat greater than an amount of heat generated by the lower semiconductor device.

10. A semiconductor package comprising:
a redistribution structure;
a lower semiconductor device arranged on the redistribution structure and including a plurality of first through electrodes each having a first horizontal width;
two connecting substrates arranged on the redistribution structure and spaced apart each other with the lower semiconductor device interposed therebetween, wherein each of the two connecting substrates includes a plurality of second through electrodes each having a second horizontal width greater than the first horizontal width; and
an upper semiconductor device arranged on the lower semiconductor device and the two connecting substrates, the upper semiconductor device electrically connected to the plurality of first through electrodes of the lower semiconductor device and the plurality of second through electrodes of each of the two connecting substrates,
wherein the lower semiconductor device comprises:
a first substrate including a first surface facing the upper semiconductor device and a second surface opposite to the first surface; and
a plurality of first upper pads arranged on the first surface of the first substrate and electrically connected to the plurality of first through electrodes,
wherein each of the two connecting substrates comprises:
a plurality of second upper pads arranged on an upper surface of each of the two connecting substrates and electrically connected to the plurality of second through electrodes, wherein a horizontal width of each of the plurality of second upper pads is greater than a horizontal width of each of the plurality of first upper pads, and
wherein the upper semiconductor device comprises:
a second substrate including a lower surface facing the lower semiconductor device;
a plurality of first pads arranged on the lower surface of the second substrate and electrically connected to the plurality of first upper pads; and
a plurality of second pads arranged on the lower surface of the second substrate and electrically connected to the plurality of second upper pads, wherein a horizontal width of each of the plurality of second pads is greater than a horizontal width of each of the plurality of first pads.

11. The semiconductor package of claim 10 , wherein the first horizontal width is about 1 μm to about 7 μm and the second horizontal width is about 10 μm to about 20 μm.

12. The semiconductor package of claim 10 , wherein the lower semiconductor device comprises
a semiconductor device layer arranged on the first surface of the first substrate.

13. The semiconductor package of claim 10 , further comprising a heat dissipation member on the upper semiconductor device.

14. The semiconductor package of claim 10 , wherein the lower semiconductor device includes a memory chip and the upper semiconductor device includes a logic chip.

15. A semiconductor package comprising:
a redistribution structure;
a lower semiconductor device arranged on the redistribution structure and including a plurality of first through electrodes each having a first horizontal width;
a connecting substrate arranged on the redistribution structure and extending along a first side of the lower semiconductor device, wherein the connecting substrate includes a plurality of second through electrodes each having a second horizontal width greater than the first horizontal width; and
an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the plurality of first through electrodes and the plurality of second through elect

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Sunkyoung
• Kim Taehwan
• Song Hyunjung
• Kim Hyoeun
• Lee Wonil
• Han Sanguk

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W40/22 Primary

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W70/635 Primary

  Through-vias · CPC title