Semiconductor package

Patent metadata

Field	Value
Publication number	US-10373935-B2
Application number	US-201816114795-A
Country	US
Kind code	B2
Filing date	Aug 28, 2018
Priority date	May 17, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor chip including a first through-electrode;
a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip, at least one of the plurality of second semiconductor chips including a second through-electrode;
a plurality of first connection bumps attached to a bottom surface of the first semiconductor chip, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer; and
a plurality of second connection bumps between the first semiconductor chip and a lowermost second semiconductor chip and between adjacent two second semiconductor chips among the plurality of second semiconductor chips, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer,
wherein the first pillar structure comprises a first pillar layer, a diffusion barrier layer, and an adhesive layer, and the second pillar structure comprises a second pillar layer and does not comprise a layer corresponding to the adhesive layer.

2. The semiconductor package of claim 1 , wherein the first pillar layer, the diffusion barrier layer and the adhesive layer are sequentially stacked on the bottom surface of the first semiconductor chip.

3. The semiconductor package of claim 2 , wherein the first pillar layer comprises a material having a Young's modulus that is lower than a Young's modulus of the second pillar layer.

4. The semiconductor package of claim 3 , wherein the first pillar layer comprises copper (Cu), and the second pillar layer comprises nickel (Ni).

5. The semiconductor package of claim 3 , wherein the diffusion barrier layer comprises nickel (Ni).

6. The semiconductor package of claim 3 , wherein the adhesive layer comprises copper (Cu).

7. The semiconductor package of claim 1 , wherein a height of the first connection bumps is higher than that of the second connection bumps.

8. The semiconductor package of claim 1 , wherein a diameter of the first pillar layer is smaller than that of the diffusion barrier layer.

9. The semiconductor package of claim 1 , wherein the first through-electrode is connected to one of the plurality of first connection bumps and to one of the plurality of second connection bumps.

10. The semiconductor package of claim 1 , further comprising:
a first molding member surrounding side surfaces of the plurality of second semiconductor chips and the plurality of second connection bumps, the first molding member being not in contact with the bottom surface of the first semiconductor chip or the plurality of first connection bumps.

11. The semiconductor package of claim 1 , wherein the second solder layer comprises a material having a melting point higher than a melting point of the first solder layer.

12. The semiconductor package of claim 1 , further comprising:
a substrate facing the bottom surface of the first semiconductor chip and electrically connected to the first semiconductor chip through the plurality of first connection bumps; and
an external connection terminal on a bottom surface of the substrate opposite to a top surface of the substrate that faces the first semiconductor chip,
wherein a width of one of the plurality of first connection bumps in a second direction, which is parallel to the top surface of the first semiconductor chip, is smaller than a width of the external connection terminal in the second direction.

13. The semiconductor package of claim 12 , wherein the substrate is an interposer or a printed circuit board (PCB), and the width of the external connection terminal in the second direction is greater than 50 μm.

14. A semiconductor package comprising:
a first semiconductor chip including a first through-electrode;
a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip, at least one of the plurality of second semiconductor chips including a second through-electrode;
a plurality of first connection bumps attached to a bottom surface of the first semiconductor, chip, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer, the first pillar structure including a first pillar layer and a diffusion barrier layer, a diameter of the first pillar layer being smaller than that of the diffusion barrier layer; and
a plurality of second connection bumps between the first semiconductor chip and a lowermost second semiconductor chip and between adjacent two second semiconductor chips among the plurality of second semiconductor chips, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer.

15. The semiconductor package of claim 14 , wherein the first solder layer includes tin (Sn) and copper (Cu), while the second solder layer includes tin (Sn) and does not includes copper (Cu).

16. The semiconductor package of claim 15 , wherein the first pillar structure include an intermediate layer which contacts the first solder layer, and the intermediate layer includes at least one of (Cu,Ni) 6 Sn 5 , (Cu,Ni) 3 Sn 4 , and (Cu,Ni) 3 Sn.

17. The semiconductor package of claim 14 , wherein a height of the first connection bumps is higher than that of the second connection bumps.

18. The semiconductor package of claim 14 , wherein a composition of the first solder layer is different from that of the second solder layer.

19. The semiconductor package of claim 14 , wherein the first through-electrode is connected to one of the plurality of first connection bumps and to one of the plurality of second connection bumps.

20. The semiconductor package of claim 19 , further comprising:
a substrate facing the bottom surface of the first semiconductor chip and electrically connected to the first semiconductor chip through the plurality of first connection bumps; and
an external connection terminal located on a bottom surface of the substrate opposite to a top surface of the substrate that faces the first semiconductor chip,
wherein a width of one of the plurality of first connection bumps in a second direction that is parallel to the top surface of the first semiconductor chip is smaller than a width of the external connection terminal in the second direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Sun-Kyoung
• Jo Cha-Jea
• Ha Soo-Hyun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title