Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)

Patent metadata

Field	Value
Publication number	US-10068874-B2
Application number	US-201415122630-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Jun 16, 2014
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.

First claim

The invention claimed is:

1. An apparatus comprising:
a first device layer comprising a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate wherein ones of the plurality of first interconnects and ones of the plurality of second interconnects are coupled to ones of the plurality of first circuit devices;
a second device layer comprising a plurality of second circuit devices juxtaposed and coupled to the other ones of the first plurality of interconnects and the second plurality of interconnects;
a memory device layer comprising a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and
contact points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects, the contact points operable for connection to an external source,
wherein one of the first device layer and the second device layer comprises GaN or GaAs devices comprising a higher voltage range than silicon-based devices of the other of the first device layer and the second device layer, and wherein the silicon-based devices have a finer pitch than a pitch of the GaN or GaAs devices.

2. The apparatus of claim 1 , wherein the plurality of first interconnects are disposed between a carrier substrate and the first device layer.

3. The apparatus of claim 1 , wherein the contact points are coupled to ones of the plurality of second interconnects.

4. The apparatus of claim 1 , wherein a plurality of memory devices are embedded in one of the plurality of first interconnects and the plurality of second interconnects.

5. The apparatus of claim 1 , wherein the contact points comprise circuit contact points, the apparatus further comprising a package comprising package contact points coupled to the circuit contact points.

Assignees

• Intel Corp

Inventors

• Nelson Donald W
• Webb M Clair
• Morrow Patrick
• Jun Kimin

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/724 Primary

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W80/314

  characterized by direct bonding of pads or other interconnections · CPC title

• H10W72/07254

  changes in dispositions · CPC title