Methods of fabricating semiconductor die assemblies

Patent metadata

Field	Value
Publication number	US-9711494-B2
Application number	US-201514600976-A
Country	US
Kind code	B2
Filing date	Jan 20, 2015
Priority date	Aug 8, 2011
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

First claim

What is claimed is:

1. A method of forming a semiconductor die assembly, comprising:
stacking at least one level of mutually laterally spaced semiconductor dice previously thinned from an initial wafer thickness and comprising integrated circuitry and having conductive through vias over unsingulated, mutually laterally separated semiconductor die locations of a semiconductor wafer previously thinned from the initial wafer thickness, each semiconductor die location comprising integrated circuitry, having conductive through vias and having conductive elements on a surface thereof opposite the at least one level of mutually laterally spaced semiconductor dice;
stacking another level of mutually laterally spaced semiconductor dice of the initial wafer thickness and comprising integrated circuitry, without conductive through vias, and of a same length and width as a length and width of the semiconductor dice of the at least one level over uppermost semiconductor dice of the at least one level with active surfaces facing toward the semiconductor wafer;
vertically operably connecting integrated circuitry of semiconductor dice in each level of a stack and integrated circuitry of an associated semiconductor die location with conductive elements between the semiconductor dice of the stack and the conductive through vias within the semiconductor dice of the at least one level and through conductive elements between a lowermost semiconductor die of the stack and the conductive through vias of the associated semiconductor die location to the conductive elements on the opposite surface of the associate semiconductor die location;
placing a dielectric material between the semiconductor dice of each stack and between a semiconductor die of each stack and the associated unsingulated die location to surround the conductive elements and substantially fill space between the semiconductor dice of each stack and between a semiconductor die of each stack and the associated unsingulated die location;
substantially simultaneously placing encapsulant material over and around each stack of semiconductor dice, contacting and covering a lateral periphery of each stack of semiconductor dice and the dielectric material with the encapsulant material extending between the stacks and onto the wafer; and
removing the encapsulant material from over the another level of semiconductor dice;
reducing the initial wafer thickness of the semiconductor dice of the another level from the initial wafer thickness to a thickness substantially the same to thicknesses of the previously thinned mutually laterally spaced semiconductor dice and the previously thinned semiconductor wafer; and
singulating the stacks of semiconductor dice through the encapsulant material extending between the stacks of semiconductor dice and through the semiconductor wafer between the mutually laterally separated semiconductor die locations.

2. The method of claim 1 , wherein stacking at least one level of semiconductor dice comprises stacking more than one level of semiconductor dice.

3. The method of claim 1 , wherein removing the encapsulant material from over the another level of semiconductor dice and reducing the initial wafer thickness of the semiconductor dice of the another level comprises back grinding.

4. The method of claim 1 , further comprising, before singulating the stacks of semiconductor dice through the encapsulant material extending between the stacks of semiconductor dice and through the wafer:
thinning the semiconductor dice of the another level;
conducting a test of each die stack; and
marking, as determined by a test, good die stack locations on exposed surfaces of the another level of semiconductor dice.

5. The method of claim 1 , further comprising orienting semiconductor dice of each stack with active surfaces thereof facing toward the wafer.

6. The method of claim 1 , wherein stacking semiconductor dice over mutually laterally separated, unsingulated semiconductor die locations comprises stacking semiconductor dice having conductive elements extending from active surfaces thereof.

7. The method of claim 1 , further comprising:
forming circuit traces extending from and in communication with conductive through vias of each unsingulated semiconductor die location over a surface of the wafer facing away from the semiconductor die stacks to test pads located over the surface of the wafer facing away from the semiconductor die stacks and laterally offset from the conductive through vias;
applying passivation over the surface and leaving only the pads and ends of conductive through vias of the unsingulated semiconductor die locations exposed: and
forming conductive elements only directly on and connected to conductive through vias of each unsingulated semiconductor die location.

8. The method of claim 1 , further comprising facing an active surface of the wafer away from the semiconductor die stacks.

9. The method of claim 1 , wherein vertically connecting semiconductor dice in each level and an associated unsingulated semiconductor die location with conductive elements is effected using one of thermocompression bonding and solder reflow.

10. A method of forming a semiconductor die assembly, comprising:
forming laterally spaced stacks of semiconductor dice, each comprising integrated circuitry, over laterally separated semiconductor die locations of a semiconductor wafer, each semiconductor die location comprising integrated circuitry, having conductive through vias and having conductive elements on an opposing side thereof from the stacks, an uppermost semiconductor die of each stack having an active surface facing the wafer and having no conductive through vias, and other semiconductor dice of each stack having conductive through vias;
vertically operably connecting integrated circuitry of semiconductor dice in each stack and integrated circuitry of a semiconductor die location under each stack with conductive elements and conductive through vias and placing a dielectric material around the conductive elements;
substantially simultaneously encapsulating each stack of semiconductor dice with a molded dielectric material over, in contact with, and between the stacks of semiconductor dice and in contact with the wafer;
removing a portion of the dielectric material extending over the stacks of semiconductor dice and thinning the uppermost semiconductor die of each stack;
conducting a test of each stack; marking, as determined by a test, good stack locations on back sides of the uppermost die of each good stack; and
severing the dielectric material and the semiconductor wafer between the stacks of semiconductor dice to form semiconductor die assemblies.

11. The method of claim 10 , wherein forming stacks of semiconductor dice comprises forming stacks comprising more than two semiconductor dice.

12. The method of claim 10 , wherein removing a portion of the dielectric material extending over the stacks of semiconductor dice and thinning the uppermost semiconductor die of each stack comprises back grinding.

13. The method of claim 10 , further comprising orienting all semiconductor dice of each stack with active surfaces thereof facing toward the wafer.

14. The method of claim 10 , wherein forming stacks of semiconductor dice over laterally separated semiconductor die locations comprises stacking semiconductor dice having conductive elements extending from active surfaces thereof.

15. The method of claim 10 , further comprising:
forming circuit traces extending from and in communication with conductive through vias of each semiconductor die location over a s

Assignees

• Micron Technology Inc

Inventors

• England Luke G
• Silvestri Paul A
• Koopmans Michel

Classifications

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title