Substrate design for semiconductor packages and method of forming same

Patent metadata

Field	Value
Publication number	US-10026671-B2
Application number	US-201414473236-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Feb 14, 2014
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edges of the first die. The device package further includes one or more second dies bonded to a first surface of the one or more RDLs and a connector element on the first surface of the one or more RDLs. The connector element has a vertical dimension greater than the one or more second dies. A package substrate is bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate.

First claim

What is claimed is:

1. A device package comprising:
a first die;
one or more redistribution layers (RDLs) electrically connected to the first die, wherein the one or more RDLs extend laterally past edges of the first die;
one or more second dies bonded to a first surface of the one or more RDLs;
a connector element on the first surface of the one or more RDLs, wherein a vertical dimension of the connector element is greater than a vertical dimension of the one or more second dies, wherein the connector element comprises:
a first portion on the first surface of the one or more RDLs, the first portion accounting for 20% to 50% of the vertical dimension of the connector element;
a second portion disposed on the first portion, the second portion being a different material than the first portion; and
a third portion disposed on the second portion, the third portion being a different material than the second portion, the third portion accounting for 20% to 50% of the vertical dimension of the connector element, the first portion, the second portion, and the third portion accounting for 100% of the vertical dimension of the connector element; and

a package substrate bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate, wherein the third portion of the connector element disposed on a first surface of the package substrate.

2. The device package of claim 1 , wherein:
the first portion comprises a first conductive pillar; and
the second portion comprises a solder region on the first conductive pillar.

3. The device package of claim 2 , wherein the third portion comprises a second conductive pillar on the solder region.

4. The device package of claim 2 , wherein a vertical dimension of the first conductive pillar is greater than a vertical dimension of the solder region.

5. The device package of claim 1 , further comprising a molded underfill surrounding the connector element.

6. The device package of claim 5 , wherein the molded underfill extends at least partially along the first surface of the package substrate and the first surface of the one or more RDLs.

7. The device package of claim 1 , further comprising a heat dissipation feature over the first die.

8. The device package of claim 1 , further comprising a molding compound extending along sidewalls of the first die and a second surface of the one or more RDLs, the second surface of the one or more RDLs opposite the first surface of the one or more RDLs.

9. The device package of claim 1 , wherein a combined vertical dimension of the first portion of the connector element and the second portion of the connector element is about 100 μm.

10. A device package comprising:
a first die;
a molding compound extending along sidewalls of the first die;
one or more redistribution layers (RDLs) on the first die and the molding compound;
a plurality of second dies bonded to a surface of the one or more RDLs opposing the first die and the molding compound, the plurality of second dies having a first vertical dimension;
a connector element on the surface of the one or more RDLs, wherein the connector element bonds a package substrate to the one or more RDLs, wherein the plurality of second dies is disposed between the one or more RDLs and the package substrate, wherein the connector element has a second vertical dimension greater than the first vertical dimension, wherein the connector element comprises:
a first conductive pillar extending from the surface of the one or more RDLs, the first conductive pillar accounting for 20% to 50% of the second vertical dimension;
a second conductive pillar extending from a surface of the package substrate facing the surface of the one or more RDLs, the second conductive pillar accounting for 20% to 50% of the second vertical dimension; and
a solder region bonding the first conductive pillar to the second conductive pillar, the solder region being a different material than the first conductive pillar and the second conductive pillar, the first conductive pillar, the second conductive pillar, and the solder region accounting for 100% of the second vertical dimension; and

a heat dissipation feature on an opposing surface of the first die as the one or more RDLs.

11. The device package of claim 10 , wherein the first conductive pillar has a height greater than the solder region.

12. The device package of claim 10 , further comprising a molded underfill surrounding the connector element.

13. The device package of claim 10 , wherein a combined vertical dimension of the first conductive pillar and the second conductive pillar is about 100 μm.

14. A method for forming a device package comprising:
forming one or more redistribution layers (RDLs) on a first die, wherein the one or more RDLs extend laterally past edges of the first die;
bonding one or more second dies to a surface of the one or more RDLs opposing the first die;
forming a first conductive pillar on the surface of the one or more RDLs;
forming a second conductive pillar on a surface of a package substrate; and
bonding the first conductive pillar to the second conductive pillar using a solder region, a vertical dimension of each of the first and second conductive pillar being from 20% to 50% of a combined vertical dimension of the first conductive pillar, the second conductive pillar, and the solder region, wherein the one or more second dies are disposed between the one or more RDLs and the package substrate after the bonding.

15. The method of claim 14 , wherein bonding the first conductive pillar to the second conductive pillar comprises:
forming the solder region on the first conductive pillar.

16. The method of claim 15 , wherein bonding the first conductive pillar to the second conductive pillar further comprises:
forming the second conductive pillar on the package substrate; and
reflowing the solder region to the second conductive pillar.

17. The method of claim 14 , further comprising forming a molded underfill surrounding the first conductive pillar and the second conductive pillar.

18. The method of claim 14 , further comprising forming a heat dissipation feature over the first die and contacting the package substrate.

19. The method of claim 14 , wherein forming the one or more RDLs on the first die comprises forming a molding compound extending along sidewalls of the first die and along a surface of the one or more RDLs facing the first die.

20. The method of claim 14 , wherein a combined vertical dimension of the first conductive pillar and the second conductive pillar is about 100 μm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Lii Mirng-Ji
• Lee Chien-Hsun
• Wang Tsung-Ding
• Cheng Jung Wei
• Liu Ming-Che
• Hou Hao-Cheng
• Lin Hung-Jen

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title