Semiconductor package

Patent metadata

Field	Value
Publication number	US-9899361-B2
Application number	US-201615254259-A
Country	US
Kind code	B2
Filing date	Sep 1, 2016
Priority date	Nov 12, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump.

First claim

What is claimed is:

1. A semiconductor package comprising:
a logic chip on a substrate;
a first memory chip on the logic chip, the first memory chip including a first active surface and a first non-active surface;
a second memory chip on the first memory chip, the first memory chip being offset from the second memory chip, the second memory chip including a second active surface and a second non-active surface, the first active surface and the second active surface oppose each other and are operatively connected to each other through a first solder bump; and
a mold layer covering the logic chip, the first memory chip, and sidewalls of the second memory chip, a non-active surface of the logic chip and the second non-active surface of the second memory chip being exposed, wherein
the first memory chip includes a first redistribution line on the first active surface,
the second memory chip includes a second redistribution line on the second active surface,
each of the first redistribution line and the second redistribution line has a bilateral symmetrical structure and a same structure, and
the logic chip is electrically connected to the first memory chip and the second memory chip through the substrate.

2. The semiconductor package of claim 1 , wherein
the second redistribution line is operatively connected to the first memory chip through the first solder bump, and the second redistribution line is operatively connected to the substrate through a bonding member, and
the bonding member is one of an interposer, a pillar, and a through-mold via (TMV).

3. The semiconductor package of claim 2 , wherein the second redistribution line comprises:
an electrode pad on a central portion of the second active surface;
a first connection pad on a first edge of the second active surface, the first connection pad operatively connected to the electrode pad; and
a second connection pad on a second edge of the second active surface, the second edge opposite to the first edge, the second connection pad operatively connected to the electrode pad, the first connection pad is operatively connected to the first memory chip, and the second connection pad is operatively connected to the substrate.

4. The semiconductor package of claim 1 , wherein
the first redistribution line is operatively connected to the second memory chip through the first solder bump, and the first redistribution line is operatively connected to the logic chip through a second solder bump.

5. The semiconductor package of claim 4 , wherein the first redistribution line comprises:
an electrode pad on a central portion of the first active surface;
a first connection pad on a first edge of the first active surface, the first connection pad operatively connected to the electrode pad; and
a second connection pad on a second edge of the first active surface, the second edge opposite to the first edge, the second connection pad operatively connected to the electrode pad, the first connection pad is operatively connected to the second memory chip, and the second connection pad is operatively connected to the logic chip.

6. A semiconductor package comprising:
a first distribution line including a first connection pad and an electrode pad, the first distribution line on a first surface of a first memory chip;
a second distribution line including a second connection pad, the second distribution line on a second surface of a second memory chip, the first surface and the second surface oppose each other by having a central portion of the first memory chip offset from a central portion of the second memory chip such that at least one of the first connection pad and the electrode pad align with the second connection pad along a vertical axis to operatively connect the first and second memory chips, the first distribution line and the second distribution line being bilaterally symmetrical and having a same structure; and
a mold layer covering a logic chip, the first memory chip, and sidewalls of the second memory chip.

7. The semiconductor package of claim 6 , wherein
the first connection pad is on a first edge of the first memory chip,
the second connection pad is on a first edge of the second memory chip, and
the first edge of the first memory chip and the first edge of the second memory chip align along the vertical axis such that the first and second memory chips are operatively connected.

8. The semiconductor package of claim 6 , wherein
the electrode pad is on the central portion of the first memory chip,
the second connection pad is on a first edge of the second memory chip, and
the central portion of the first memory chip and the first edge of the second memory chip align along the vertical axis such that the first and second memory chips are operatively connected.

9. The semiconductor package of claim 7 , further comprising:
a solder bump between the first edge of the first memory chip and the first edge of the second memory chip, the solder bump operatively connecting the first and second memory chips and the first connection pad aligning with the second connection pad along the vertical axis.

10. The semiconductor package of claim 8 , further comprising:
a solder bump between the central portion of the first memory chip and the first edge of the second memory chip, the solder bump operatively connecting the first and second memory chips and the electrode pad aligns with the second connection pad along the vertical axis.

11. The semiconductor package of claim 1 , wherein the first active surface and the second active surface are mirror-symmetrical.

12. The semiconductor package of claim 1 , further comprising:
a heat dissipation layer on the exposed second non-active surface of the second memory chip, and the mold layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyoungjoon
• Park Kwangil
• Kwon Seok Hong
• Park Chulsung
• Seo Eunsung
• Lee Heejin
• Park Kijong

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title