Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

Patent metadata

Field	Value
Publication number	US-11967948-B2
Application number	US-202217839386-A
Country	US
Kind code	B2
Filing date	Jun 13, 2022
Priority date	Jul 11, 2005
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

First claim

What is claimed is:

1. A method comprising:
controlling a first switch circuit to set the first switch circuit to be in either a first state or a second state, wherein the first switch circuit comprises a first transistor; and
electrically biasing a body of the first transistor with a bias signal during at least a portion of a duration when the first switch circuit is in the second state to control accumulated charge in the body.

2. The method of claim 1 , wherein the bias signal comprises a bias voltage that is substantially more negative than ground.

3. The method of claim 1 , wherein the accumulated charge is associated with carriers having a polarity opposite a polarity of carriers in a drain and a source of the first transistor when the first transistor is operated in an on state.

4. The method of claim 1 , further comprising selectively connecting, by the first switch circuit, a first port to a second port based on a state of the first switch circuit.

5. The method of claim 4 , wherein the selectively connecting comprises:
connecting the first port to the second port when the switch circuit is in the first state; and
not connecting the first port to the second port when the switch circuit is in the second state.

6. The method of claim 5 , wherein the second port is connected to ground.

7. The method of claim 1 , further comprising:
passing a signal from a first port to a second port via the first switch circuit during at least a portion of a duration when the first switch circuit is in the first state; and
not passing the signal from the first port to the second port via the first switch circuit during at least a portion of a duration when the first switch circuit is in the second state.

8. The method of claim 1 , further comprising:
controlling a second switch circuit to set the first switch circuit to be in either a third state or a fourth state, wherein the second switch circuit comprises a second transistor; and
electrically biasing a body of the second transistor with a bias signal during at least a portion of a duration when the second switch circuit is in the fourth state to control accumulated charge in the body of the second transistor.

9. The method of claim 8 , wherein:
the controlling the first switch circuit and the controlling the second switch circuit are based on a first switch control signal; and
when the first switch control signal is enabled, the first switch circuit is in the first state and the second switch circuit is in the fourth state.

10. The method of claim 9 , wherein the controlling the first switch circuit and the controlling the second switch circuit are further based on a second switch control signal, wherein, when the second switch control signal is enabled, the first switch circuit is in the second state and the second switch circuit is in the third state, wherein the first state is an on state of the first switch circuit, wherein the second state is an off state of the first switch circuit, wherein the third state is an on state of the second switch circuit, and wherein the fourth state is an off state of the second switch circuit.

11. The method of claim 8 , further comprising:
not shunting a first port to a ground port via the second switch circuit during at least a portion of a duration when the first switch circuit is in the first state; and
shunting the first port to the ground port via the second switch circuit during at least a portion of a duration when the first switch circuit is in the second state.

12. A switch comprising:
a control circuit configured to generate one or more switch control signals; and
a first switch circuit configured to be in either a first state or a second state based on the one or more switch control signals, wherein the first switch circuit comprises a first transistor having a body configured to receive a bias signal during at least a portion of a duration when the first switch circuit is in the second state to control accumulated charge in the body.

13. The switch of claim 12 , wherein the bias signal comprises a bias voltage that is substantially more negative than ground.

14. The switch of claim 12 , wherein the first transistor comprises an n-type metal oxide semiconductor field effect transistor.

15. The switch of claim 12 , wherein the accumulated charge is associated with carriers having a polarity opposite a polarity of carriers in a drain and a source of the first transistor when the first transistor is operated in an on state.

16. The switch of claim 12 , wherein the first switch circuit is configured to:
couple a first port to a second port when the first switch circuit is in the first state; and
not couple the first port to the second port when the first switch circuit is in the second state.

17. The switch of claim 12 , further comprising a second switch circuit configured to be in either a third state or a fourth state based on the one or more switch control signals, wherein the second switch circuit comprises a second transistor having a body configured to receive a bias signal during at least a portion of a duration when the second switch circuit is in the fourth state to control accumulated charge in the body of the second transistor.

18. The switch of claim 17 , wherein the one or more switch control signals comprise a first switch control signal, wherein, when the first switch control signal is enabled, the first switch circuit is configured to be in the first state and the second switch circuit is configured to be in the fourth state.

19. The switch of claim 18 , wherein the one or more switch control signals further comprise a second switch control signal, wherein, when the second switch control signal is enabled, the first switch circuit is configured to be in the second state and the second switch circuit is configured to be in the third state, wherein the first state is an on state of the first switch circuit, wherein the second state is an off state of the first switch circuit, wherein the third state is an on state of the second switch circuit, and wherein the fourth state is an off state of the second switch circuit.

20. The switch of claim 17 , wherein the second switch circuit is configured to:
not shunt a first port to a ground port during at least a portion of a duration when the first switch circuit is in the first state; and
shunt the first port to the ground port during at least a portion of a duration when the first switch circuit is in the second state.

Assignees

• Psemi Corp

Inventors

• Brindle Christopher N
• Stuber Michael A
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George
• Welstand Robert B
• Burgener Mark L

Classifications

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/6711

  by using electrodes contacting the supplementary regions or layers · CPC title