Method and apparatus for use in improving linearity of mosfets using an accumulated charge sink

Patent metadata

Field	Value
Publication number	US-2020295751-A1
Application number	US-202016853688-A
Country	US
Kind code	A1
Filing date	Apr 20, 2020
Priority date	Jul 11, 2005
Publication date	Sep 17, 2020
Grant date	—

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

First claim

1 . (canceled)

2 - 14 . (canceled)

15 . A method of fabricating an RF switch comprising:
fabricating an integrated circuit (IC) that includes the RF switch; wherein the fabricating includes forming at least a plurality of N-type metal oxide semiconductor field effect transistors (NMOSFETs) by forming a source, a drain, a gate and a body for respective NMOSFETs of the plurality in a silicon layer of a substrate; wherein the fabricating further includes fabricating one or more layers of metallization over the silicon layer; wherein the one or more layers of metallization to couple the plurality of NMOSFETs into a stack to pass an RF signal through the stack of NMOSFETs in an ON state of the stack of NMOSFETs in accordance with RF switch operation; wherein the one or more layers of metallization to couple the plurality of NMOSFETs of the stack to not pass an RF signal through the stack of NMOSFETs in an OFF state of the stack of NMOSFETs in accordance with RF switch operation; and wherein the one or more layers of metallization to couple an electrical bias to the body of the respective NMOSFETs, in accordance with RF switch operation, at least in a portion of the OFF state of the stack to have a DC voltage level substantially more negative than a lowest voltage level of the following: ground, a DC voltage level of the source of the respective NMOSFETs, and a DC voltage level of the drain of the respective NMOSFETs.

16 . The method of claim 15 , wherein the substrate comprises a silicon on insulator (SOI) substrate.

17 . The method of claim 16 , wherein the forming the source, the drain, the gate and the body for the respective NMOSFETs of the plurality in the silicon layer of the SOI substrate comprises:
forming the gate from a conductive layer and an oxide layer on the silicon layer of the SOI substrate; and forming two N+ regions in the silicon layer of the SOI substrate via ion implantation or diffusion to form the source, the drain, and the body.

18 . The method of claim 16 , wherein the forming the gate from the conductive layer comprises forming the gate from a polysilicon gate layer.

19 . The method of claim 17 , wherein the silicon layer of the SOI substrate comprises a thin-film silicon layer with a thickness of less than 150 nm.

20 . The method of claim 19 , wherein the forming the two N+ regions comprises forming the two N+ regions to extend through the silicon layer to an insulating layer of the SOI substrate.

21 . The method of claim 16 , wherein the fabricating further includes forming an accumulated charge sink (ACS) in direct physical contact with the body of the respective NMOSFETs, the ACS being formed in the silicon layer.

22 . The method of claim 21 , wherein the fabricating further includes forming an electrical contact region for the ACS, the electrical contact region comprising a P+ doped region formed in the silicon layer via ion implantation or diffusion.

23 . The method of claim 22 , wherein the electrical contact region for the ACS is formed in the silicon layer a selected distance away from the body of the respective NMOSFETs.

24 . The method of claim 21 , wherein the fabricating further includes fabricating a diode in the silicon layer of the SOI substrate and wherein at least one of the fabricated layers of metallization over the silicon layer couples the diode to the ACS, for the respective NMOSFETs.

25 . The method of claim 16 , wherein the fabricating comprises fabricating a negative voltage generator circuit to generate the DC voltage level to have the voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the respective NMOSFETs, and the DC voltage level of the drain for the respective NMOSFETs.

26 . The method of claim 25 , wherein the fabricating the negative voltage generator circuit comprises fabricating the negative voltage generator circuit to comprise a charge pump.

27 . The method of claim 25 , wherein the fabricating the negative voltage generator comprises fabricating the negative voltage generator circuit to generate the DC voltage level to have the voltage level at least one volt more negative than the lowest voltage level of the following: ground, the DC voltage level of the source for the respective NMOSFETs, and the DC voltage level of the drain for the respective NMOSFETs.

Assignees

• Psemi Corp

Inventors

• Brindle Christopher N
• Stuber Michael A
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George
• Welstand Robert B
• Burgener Mark L

Classifications

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/6711

  by using electrodes contacting the supplementary regions or layers · CPC title