Switch circuit and method of switching radio frequency signals

Patent metadata

Field	Value
Publication number	US-10790820-B2
Application number	US-201916679760-A
Country	US
Kind code	B2
Filing date	Nov 11, 2019
Priority date	Oct 10, 2001
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The inventive RF switch provides improvements in insertion loss, switch isolation, and switch compression.

First claim

What is claimed is:

1. A method of operating an RF circuit in which at least one integrated circuit chip comprises the RF circuit, wherein the RF circuit includes a switch transistor grouping comprising a first plurality of N-type metal oxide semiconductor field effect transistors (NMOSFETs) arranged in a first stacked configuration, the switch transistor grouping via a switch transistor grouping control signal either to pass or to not pass an RF signal between a first RF node and a second RF node, the second RF node being coupled to the first RF node, and a shunt transistor grouping comprising a second plurality of NMOSFET transistors arranged in a second stacked configuration, the shunt transistor grouping via a shunt transistor grouping control signal either to shunt the first RF node coupled to ground or to isolate the first RF node from ground, the at least one integrated circuit chip further comprising an integrated digital control logic circuit to provide the one or more control signals to the RF circuit and a negative voltage generator circuit comprising a charge pump to generate a voltage substantially negative with respect to ground, the method comprising:
passing the RF signal between the first RF node and the second RF node in a switch ON state using the switch transistor grouping of the RF circuit;
generating the voltage substantially negative with respect to ground using the negative voltage generator circuit comprising the charge pump;
controlling the shunt transistor grouping in a shunt OFF state by the shunt transistor grouping control signal, that further comprises the substantially negative generated voltage; and
isolating the first RF node from ground in the shunt OFF state of the shunt transistor grouping of the RF circuit.

2. The method of claim 1 , wherein the passing and the isolating take place at least partially concurrently.

3. The method of claim 1 , wherein the controlling the shunt transistor grouping in the shunt OFF state comprises electrically biasing the NMOSFET transistors of the second plurality, the electrically biasing, for respective NMOSFET transistors of the second plurality, being via at least one gate-coupled resistor.

4. The method of claim 3 , wherein the electrically biasing via the at least one gate-coupled resistor comprises electrically biasing via at least one resistor having a resistance of at least 30 kohms.

5. The method of claim 3 , wherein the electrically biasing the NMOSFET transistors of the second plurality comprises electrically biasing the NMOSFET transistors of the second plurality arranged in the second stacked configuration to withstand a voltage across the second stacked configuration of NMOSFET transistors having a voltage magnitude greater than a breakdown voltage of an individual NMOSFET transistor in the second stacked configuration.

6. The method of claim 1 , wherein the passing the RF signal between the first RF node and the second RF node comprises passing the RF signal in the at least one integrated circuit chip implemented in silicon on insulator (SOI) technology.

7. The method of claim 6 , wherein the passing the RF signal between the first RF node and the second RF node comprises passing the RF signal in a thin film silicon layer.

8. The method of claim 7 , wherein the passing the RF signal between the first RF node and the second RF node comprises passing the RF signal in the thin film silicon layer having a thickness of less than 150 nm.

9. The method of claim 7 , wherein the passing the RF signal between the first RF node and the second RF node comprises passing the RF signal in the at least one integrated circuit chip implemented with at least the thin film silicon layer on an insulating layer in which sources and drains of the NMOSFET transistors extend through the entire thickness of the thin film silicon layer to the insulating layer.

10. The method of claim 7 , wherein the passing the RF signal between the first RF node and the second RF node comprises passing the RF signal with increased electrical isolation between the RF circuit and the negative voltage generator circuit at least in part via the SOI technology comprising at least an insulating layer.

11. The method of claim 10 , wherein the passing the RF signal between the first RF node and the second RF node comprises passing the RF signal with increased electrical isolation at least so as to be capable to use the at least one integrated circuit chip in an at least GSM compliant cellular wireless communication system.

12. The method of claim 6 , wherein the isolating the first RF node from ground comprises isolating a high power RF signal at the first RF node from ground.

13. The method of claim 12 , wherein the isolating the high power RF signal comprises isolating an at least GSM compliant RF signal.

14. The method of claim 6 , wherein the passing the RF signal comprises passing an at least GSM compliant RF signal.

15. The method of claim 1 , wherein the passing the RF signal between the first RF node and the second RF node comprises passing the RF signal during use of the at least one integrated circuit chip in a cellular wireless communication system.

16. A method of operating an RF circuit in which at least one integrated circuit chip comprises the RF circuit, wherein the RF circuit includes a switch transistor grouping comprising a first plurality of N-type metal oxide semiconductor field effect transistors (NMOSFETs) arranged in a first stacked configuration, the switch transistor grouping via a switch transistor grouping control signal either to pass or to not pass an RF signal between a first RF node and a second RF node, the second RF node being coupled to the first RF node, and a shunt transistor grouping comprising a second plurality of NMOSFET transistors arranged in a second stacked configuration, the shunt transistor grouping via a shunt transistor grouping control signal either to shunt the first RF node coupled to ground or to isolate the first RF node from ground, the at least one integrated circuit chip further comprising an integrated digital control logic circuit to provide the one or more control signals to the RF circuit and a negative voltage generator circuit including a charge pump to generate a voltage substantially negative with respect to ground, the method comprising:
shunting the first RF node to ground using the shunt transistor grouping of the RF circuit in a shunt ON state of the shunt transistor grouping of the RF circuit;
generating the voltage substantially negative with respect to ground using the negative voltage generator circuit comprising the charge pump;
controlling the switch transistor grouping in a switch OFF state by the switch transistor grouping control signal, that further comprises the substantially negative generated voltage; and
not passing the RF signal between the first RF node and the second RF node in the switch OFF state of the switch transistor grouping of the RF circuit.

17. The method of claim 16 , wherein the shunting and the not passing take place at least partially concurrently.

18. The method of claim 16 , wherein the controlling the switch transistor grouping in the switch OFF state comprises electrically biasing the NMOSFET transistors of the first plurality, the electrically biasing, for respective NMOSFET transistors of the first plurality, being via at least one gate-coupled resistor.

19. The method of claim 18 , wherein the electrically biasing the NMOSFET transistors of the first plurality comprises electrically biasing the NMOSFET transis

Assignees

• Psemi Corp

Inventors

• Burgener Mark L
• Cable James S
• Benton Robert H

Classifications

• H01P1/15 Primary

  by semiconductor devices · CPC title

• H03K17/063

  in field-effect transistor switches · CPC title

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03K2017/0803

  against radiation hardening · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title