Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

Patent metadata

Field	Value
Publication number	US-10797690-B2
Application number	US-201916590262-A
Country	US
Kind code	B2
Filing date	Oct 1, 2019
Priority date	Jul 11, 2005
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

First claim

What is claimed is:

1. A method of operating a module, the module including at least one integrated circuit chip comprising a plurality of series N-type metal oxide semiconductor (NMOS) field effect transistors configured in a series connected stack configuration that comprises at least one series NMOS field effect transistor including a body, the at least one series NMOS field effect transistor either to pass an RF signal in a series enable state or to not pass the RF signal in a series disable state, the method further comprising:
electrically biasing the body of the at least one series NMOS field effect transistor of the module in the series disable state to have a voltage level substantially more negative than the lowest voltage level of the following: ground, a DC voltage level of a source of the at least one series NMOS field effect transistor of the module, and a DC voltage level of a drain of the at least one series NMOS field effect transistor of the module.

2. The method of claim 1 , wherein the electrically biasing the body of the at least one series NMOS field effect transistor in the series disable state comprises respectively electrically biasing a plurality of bodies of the plurality of series NMOS field effect transistors in the series disable state.

3. The method of claim 2 , wherein the respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors for a circuit operable in an RF switch on the at least one integrated circuit chip, which is implemented in silicon on insulator (SOI) technology.

4. The method of claim 3 , wherein the respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in the SOI technology, comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in the SOI technology, comprising a substrate including a thin film silicon layer with a thickness less than 150 nm.

5. The method of claim 3 , wherein the respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in the SOI technology, comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in the SOI technology, comprising a thin film silicon layer on an insulating layer with sources and drains of respective NMOS field effect transistors of the plurality extending through the entire thickness of the thin film silicon layer to the insulating layer.

6. The method of claim 3 , wherein the electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistor in the series disable state comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors in the series disable state to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the sources of the plurality of series NMOS field effect transistors of the module, and the DC voltage level of the drains of the plurality of series NMOS field effect transistors of the module, comprises at least improving the linearity of the plurality of series NMOS field effect transistors.

7. The method of claim 2 , wherein the at least one integrated circuit chip comprises one or more additional pluralities of series N-type metal oxide semiconductor (NMOS) field effect transistors respectively in one or more additional series connected stack configurations;
and further comprising: respectively electrically biasing one or more additional pluralities of bodies of the one or more additional pluralities of series NMOS field effect transistors in the series disable state to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the sources of the one or more additional pluralities of series NMOS field effect transistors of the module, and the DC voltage level of the drains of the one or more additional pluralities of series NMOS field effect transistors of the module.

8. The method of claim 7 , wherein the respectively electrically biasing the one or more additional pluralities of bodies of the one or more additional pluralities of series NMOS field effect transistors comprises respectively electrically biasing the one or more additional pluralities of bodies of the one or more additional pluralities of series NMOS field effect transistors for a circuit operable in an RF switch on the at least one integrated circuit chip, which is implemented in silicon on insulator (SOI) technology.

9. The method of claim 7 , wherein the respectively electrically biasing the one or more additional pluralities of bodies of the one or more additional pluralities of series NMOS field effect transistors comprises at least improving the linearity of the one or more additional pluralities of series NMOS field effect transistors.

10. A method of operating a communication device, the communication device including at least one integrated circuit chip comprising a plurality of series N-type metal oxide semiconductor (NMOS) field effect transistors configured in a series connected stack configuration that comprises at least one series NMOS field effect transistor including a body, the at least one series NMOS field effect transistor either to pass an RF signal in a series enable state or to not pass the RF signal in a series disable state, the method further comprising:
electrically biasing the body of the at least one series NMOS field effect transistor of the communication device in the series disable state to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one series NMOS field effect transistor of the communication device, and the DC voltage level of the drain of the at least one series NMOS field effect transistor of the communication device.

11. The method of claim 10 , wherein the electrically biasing the body of the at least one series NMOS field effect transistor in the disable state comprises respectively electrically biasing a plurality of bodies of the plurality of series NMOS field effect transistors in the series disable state.

12. The method of claim 11 , wherein the respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors for a circuit operable in an RF switch on the at least one integrated circuit chip, which is implemented in silicon insulator (SOI) technology.

13. The method of claim 12 , wherein the respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in SOI technology, comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in the SOI technology, comprising a substrate including a thin film silicon layer with a thickness

Assignees

• Psemi Corp

Inventors

• Brindle Christopher N
• Stuber Michael A
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George
• Welstand Robert B
• Burgener Mark L

Classifications

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/675

  Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/6711

  by using electrodes contacting the supplementary regions or layers · CPC title